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21. 发明授权

US5630905A Method of fabricating quantum bridges by selective etching of superlattice structures 失效
标题翻译：通过选择性蚀刻超晶格结构制造量子桥的方法
公开(公告)号：US5630905A
公开(公告)日：1997-05-20
申请号：US465493
申请日：1995-06-05
申请人： William T. Lynch , Kang L. Wang , Martin O. Tanner
发明人： William T. Lynch , Kang L. Wang , Martin O. Tanner
IPC分类号： H01L29/12 , H01L31/0352 , H01L33/04 , H01L33/06 , H01L21/20
CPC分类号： H01L33/06 , B82Y10/00 , B82Y20/00 , H01L29/125 , H01L31/0352 , H01L31/035254 , H01L33/04
摘要： A quantum bridge structure including wires of a semiconductor material such as silicon which are formed by selectively etching a superlattice of alternating layers of at least two semiconductor materials. The quantum bridge is useful as a photo emission device, a photo detector device, and a chemical sensor. The wires exhibit improved electrical conduction properties due to decreased Coulomb scattering.
摘要翻译：包括通过选择性地蚀刻至少两种半导体材料的交替层的超晶格而形成的诸如硅的半导体材料的导线的量子桥结构。量子桥可用作光发射器件，光电检测器件和化学传感器。由于库仑散射减少，电线表现出改善的导电性能。

22. 发明授权

US5449642A Method of forming metal-disilicide layers and contacts 失效
标题翻译：形成金属二硅化物层和接触的方法
公开(公告)号：US5449642A
公开(公告)日：1995-09-12
申请号：US227659
申请日：1994-04-14
申请人： Teh Y. Tan , Gary E. McGuire , William T. Lynch
发明人： Teh Y. Tan , Gary E. McGuire , William T. Lynch
IPC分类号： H01L21/285 , H01L21/336 , H01L23/482 , H01L29/45 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66772 , H01L21/28518 , H01L23/4825 , H01L29/458 , H01L2924/0002
摘要： A method of forming a metal-disilicide (MSi.sub.2) film from a silicon-on-insulator (SOI) substrate having an insulating underlayer and a silicon outerlayer includes the formation of a first capping layer on a portion of the silicon outerlayer. The first capping layer preferably includes titanium and a preselected metal (M) such as cobalt. A step is then performed to convert a first portion of the silicon outerlayer to metal-disilicide. This step is preferably accomplished by a rapid thermal annealing step. Thereafter, a second capping layer is formed on the metal-disilicide layer. The second capping layer preferably includes titanium and metal-monosilicide (MSi). Next, a step is performed to convert a second portion of the silicon outerlayer, beneath the first portion, to metal-disilicide while preventing phase-reversal of the already formed metal-disilicide layer to metal-monosilicide. This step is preferably accomplished by a rapid thermal annealing step as well. The method can preferably be used to form low resistance metal-disilicide contacts to active regions of SOI electronic devices.
摘要翻译：从具有绝缘底层和硅外层的绝缘体上硅（SOI）衬底形成金属二硅化物（MSi2）膜的方法包括在硅外层的一部分上形成第一覆盖层。第一覆盖层优选包括钛和预选的金属（M）如钴。然后进行步骤以将硅外层的第一部分转化为金属二硅化物。该步骤优选通过快速热退火步骤完成。此后，在金属二硅化物层上形成第二覆盖层。第二盖层优选包括钛和金属一硅化物（MSi）。接下来，执行步骤，以将第二部分之下的硅外层的第二部分在第一部分之下转化为金属二硅化物，同时防止已经形成的金属二硅化物层与金属一硅化物相反相。该步骤也优选通过快速热退火步骤完成。该方法可优选用于形成低电阻金属二硅化物与SOI电子器件的有源区的接触。

23. 发明授权

US4896108A Test circuit for measuring specific contact resistivity of self-aligned contacts in integrated circuits 失效
标题翻译：用于测量集成电路中自对准触点的特定接触电阻的测试电路
公开(公告)号：US4896108A
公开(公告)日：1990-01-23
申请号：US224512
申请日：1988-07-25
申请人： William T. Lynch , Kwok K. Ng
发明人： William T. Lynch , Kwok K. Ng
IPC分类号： G01R31/26 , G01R27/14 , G01R31/27 , H01L21/28 , H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , G01R27/14 , G01R31/275 , H01L2924/3011
摘要： A test circuit is described for measuring the specific contact resistivity r.sub.c of self-aligned electrodes contacting underlying diffused regions at a major surface of an underlying semiconductor wafer, as well as the sheet (lateral) resistance r.sub.s of the underlying diffused regions in some embodiments. The test circuit illustratively includes a pair of test MOS or other type of transistors advantageously made by a self-aligned metallization process simultaneously with the other MOS or other type of transistors to be tested. The two test transistors share a common diffused region, a self-aligned common controlled electrode contacting a diffused region underneath it, and a common control electrode. During test operation, both est transistors are kept ON by means of an applied above-threshold control voltage, while a current source forces current through one of the transistors. The resulting voltage, developed across the common controlled electrode and the controlled electrode of the other transistor is a measure of the specific contact resistivity thereat.

24. 发明授权

US4794091A Method of making high-performance dram arrays including trench capacitors 失效
标题翻译：制造包括沟槽电容器的高性能电容阵列的方法
公开(公告)号：US4794091A
公开(公告)日：1988-12-27
申请号：US121556
申请日：1987-11-17
申请人： William T. Lynch
发明人： William T. Lynch
IPC分类号： G11C11/401 , H01L21/76 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/94 , H01L21/302
CPC分类号： H01L27/10861 , H01L27/10829 , H01L29/945
摘要： Parallel elongated trenches in a silicon substrate are utilized to form multiple distinct memory cell capacitors on each continuous wall of each trench. Chanstops are formed between adjacent capacitors to achieve electrical isolation. A separate word line overlies each trench wall and is connected via respective MOS transistors to the spaced-apart capacitors formed on the wall. A reliable high-density memory characterized by excellent performance is thereby realized.
摘要翻译：硅衬底中的平行细长沟槽用于在每个沟槽的每个连续壁上形成多个不同的存储单元电容器。在相邻电容器之间形成节流阀以实现电隔离。单独的字线覆盖每个沟槽壁，并且经由各个MOS晶体管连接到形成在壁上的间隔开的电容器。从而实现了性能优异的可靠的高密度存储器。

25. 发明授权

US4766090A Methods for fabricating latchup-preventing CMOS device 失效
标题翻译：用于制造防止闭锁的CMOS器件的方法
公开(公告)号：US4766090A
公开(公告)日：1988-08-23
申请号：US933631
申请日：1986-11-21
申请人： Gerald A. Coquin , William T. Lynch , Louis C. Parrillo
发明人： Gerald A. Coquin , William T. Lynch , Louis C. Parrillo
IPC分类号： H01L21/763 , H01L21/425
CPC分类号： H01L21/763
摘要： A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed.The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
摘要翻译：公开了一种新的CMOS器件，其避免了在小于10μm的器件的n沟道FET和p沟道FET之间实现间隔而闭锁，以及制造该选择的方法。本发明的器件，其形成在包括相对重掺杂的体区域的衬底中，该衬底包括相对较薄的适中掺杂层，其包括延伸穿过层的一部分的多晶硅填充沟槽，其中n沟道FET和p沟道FET之间装置。本发明的器件还包括从沟槽的底部延伸到体区的相对重掺杂的区域。掺杂多晶硅的沟槽与相对重掺杂的区域和体区两者结合防止闭锁。

26. 发明授权

US4656730A Method for fabricating CMOS devices 失效
标题翻译：制造CMOS器件的方法
公开(公告)号：US4656730A
公开(公告)日：1987-04-14
申请号：US674274
申请日：1984-11-23
申请人： William T. Lynch , Louis C. Parrillo
发明人： William T. Lynch , Louis C. Parrillo
IPC分类号： H01L21/76 , H01L21/033 , H01L21/225 , H01L21/762 , H01L21/763 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L21/38 , H01L21/461
CPC分类号： H01L21/76232 , H01L21/033 , H01L21/2253 , H01L21/76202 , H01L21/763 , H01L21/823892 , H01L27/0921 , Y10S438/938
摘要： A new method for fabricating CMOS devices, as well as the resulting devices, is disclosed. The method involves incorporating dopants into a semiconductor substrate through a region of the substrate surface, and diffusing the implanted dopants into the substrate to form a tub. Prior to the diffusion step, a trench is formed in, and extending beneath, the surface which partially or completely encircles the region. The trench serves to prevent the formation, or reduce the size, of a relatively low dopant concentration region, which would otherwise lead to undesirable leakage currents in the completed CMOS device, and prevents latchup.
摘要翻译：公开了一种用于制造CMOS器件的新方法以及所得到的器件。该方法包括通过衬底表面的区域将掺杂剂掺入到半导体衬底中，以及将注入的掺杂剂扩散到衬底中以形成桶。在扩散步骤之前，在部分地或完全地环绕该区域的表面上形成沟槽并在其下方延伸。该沟槽用于防止相对低的掺杂剂浓度区域的形成或减小尺寸，否则这将导致完成的CMOS器件中的不期望的泄漏电流，并且防止闭锁。

27. 发明授权

US4485550A Fabrication of schottky-barrier MOS FETs 失效
标题翻译：肖特基势垒MOS FET的制造
公开(公告)号：US4485550A
公开(公告)日：1984-12-04
申请号：US401142
申请日：1982-07-23
申请人： Conrad J. Koeneke , Martin P. Lepselter , William T. Lynch
发明人： Conrad J. Koeneke , Martin P. Lepselter , William T. Lynch
IPC分类号： H01L27/088 , H01L21/266 , H01L21/285 , H01L21/8234 , H01L27/092 , H01L29/10 , H01L29/47 , H01L29/78 , H01L29/872 , H01L21/28
CPC分类号： H01L27/092 , H01L21/266 , H01L21/28537 , H01L29/1087 , H01L29/47 , H01L29/7839
摘要： Schottky-barrier MOS and CMOS devices are significantly improved by selectively doping the regions surrounding the Schottky-barrier source and drain contacts. For p-channel devices, acceptor doping is carried out in either a one-step or a two-step ion implantation procedure. For n-channel devices, donor doping is carried out in a two-step procedure. In each case, current injection into the channel is enhanced and leakage to the substrate is reduced while still maintaining substantial immunity to parasitic bipolar transistor action (MOS devices) and to latchup (CMOS devices).
摘要翻译：通过选择性掺杂围绕肖特基势垒源极和漏极触点的区域，肖特基势垒MOS和CMOS器件得到显着改善。对于p沟道器件，受体掺杂以一步或两步离子注入法进行。对于n沟道器件，施主掺杂是以两步法进行的。在每种情况下，电流注入到通道中都会增强，并且对基板的泄漏减小，同时仍然保持对寄生双极晶体管作用（MOS器件）和闭锁（CMOS器件）的实质性抗扰性。

28. 发明授权

US4432132A Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features 失效
标题翻译：通过活性氧离子蚀刻形成侧壁氧化物层，以确定亚微米特征
公开(公告)号：US4432132A
公开(公告)日：1984-02-21
申请号：US328368
申请日：1981-12-07
申请人： Eliezer Kinsbron , William T. Lynch
发明人： Eliezer Kinsbron , William T. Lynch
IPC分类号： H01L29/78 , H01L21/033 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/3213 , H01L21/336 , H01L21/42 , H01L21/423 , C23C15/00
CPC分类号： H01L29/66643 , H01L21/033 , H01L21/28132 , H01L21/31116 , H01L21/31604 , H01L21/32136 , H01L21/32137 , H01L29/66575
摘要： This invention involves the defining of a submicron feature (21 or 93) in a structure, typically an insulated gate field effect transistor structure (30, 40, or 110). This feature is defined by a sidewall oxide protective masking layer (21 or 71) formed by reactive oxygen ion etching of the structure being built at a time when an exposed surface thereof in the vicinity of the sidewall contains atoms of a material--for example, silicon or aluminum--which combine with the oxygen ions to form the sidewall oxide layer.
摘要翻译：本发明涉及在通常为绝缘栅场效应晶体管结构（30,40或110）的结构中限定亚微米特征（21或93）。该特征由在其侧壁附近的暴露表面包含材料原子的时候构建的结构的活性氧离子蚀刻形成的侧壁氧化物保护掩模层（21或71）限定，例如，硅或铝 - 其与氧离子结合以形成侧壁氧化物层。

29. 发明授权

US07809698B1 System and method remapping identifiers to secure files 有权
标题翻译：系统和方法将标识符重新映射到安全文件
公开(公告)号：US07809698B1
公开(公告)日：2010-10-05
申请号：US10746300
申请日：2003-12-24
申请人： Richard E. Salz , Eugene Kuznetsov , Cyrus A. Dolph , William T. Lynch , Anthony M. French
发明人： Richard E. Salz , Eugene Kuznetsov , Cyrus A. Dolph , William T. Lynch , Anthony M. French
IPC分类号： G06F7/00 , G06F15/16
CPC分类号： G06F21/6227 , H04L63/123 , H04L67/02 , H04L67/2819 , H04L67/2823 , Y10S707/927
摘要： A flexible system for associating a data stream with one or more secure control files based on mapping self-declared identifiers to trusted identifiers. It has particular application in relation to XML documents, XML Schema, XPath/XSLT/XQuery and WSDL file processing. Control file identifiers are detected in a data stream and transformed to map to new identifiers which are correlated to locations which are more secure and/or accessible. Optionally, copies of the control files are then stored and maintained at the new locations.
摘要翻译：一种用于将数据流与一个或多个安全控制文件相关联的灵活系统，其基于将自身声明的标识符映射到可信标识符。它具有与XML文档，XML Schema，XPath / XSLT / XQuery和WSDL文件处理相关的特殊应用。在数据流中检测控制文件标识符，并将其转换为映射到与更安全和/或可访问的位置相关联的新标识符。可选地，控制文件的副本然后被存储并保持在新的位置。

30. 发明授权

US4647957A Latchup-preventing CMOS device 失效
标题翻译：防闩锁CMOS器件
公开(公告)号：US4647957A
公开(公告)日：1987-03-03
申请号：US857392
申请日：1986-04-21
申请人： Gerald A. Coquin , William T. Lynch , Louis C. Parrillo
发明人： Gerald A. Coquin , William T. Lynch , Louis C. Parrillo
IPC分类号： H01L21/763 , H01L27/092 , H01L27/02 , H01L29/06
CPC分类号： H01L27/0921 , H01L21/763
摘要： A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed. The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.
摘要翻译：公开了一种新的CMOS器件，其避免了在小于10μm的器件的n沟道FET和p沟道FET之间实现间隔而闭锁，以及制造该选择的方法。本发明的器件，其形成在包括相对重掺杂的体区域的衬底中，该衬底包括相对较薄的适中掺杂层，其包括延伸穿过层的一部分的多晶硅填充沟槽，其中n沟道FET和p沟道FET之间装置。本发明的器件还包括从沟槽的底部延伸到体区的相对重掺杂的区域。掺杂多晶硅的沟槽与相对重掺杂的区域和体区两者结合防止闭锁。

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