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21. 发明申请

US20090216985A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING 有权
标题翻译：用于动态选择记忆镜的方法，系统和计算机程序产品
公开(公告)号：US20090216985A1
公开(公告)日：2009-08-27
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/02
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

22. 发明申请

US20090193203A1 System to Reduce Latency by Running a Memory Channel Frequency Fully Asynchronous from a Memory Device Frequency 失效
标题翻译：通过运行存储器通道频率从存储器件频率完全异步的系统来减少延迟
公开(公告)号：US20090193203A1
公开(公告)日：2009-07-30
申请号：US12019043
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F12/00
CPC分类号： G06F13/4243
摘要： A memory system is provided that reduces latency by running a memory channel fully asynchronous from a memory device frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. The first operating frequency is a maximum designed operating frequency of the memory channel and the first operating frequency is independent of the second operating frequency.
摘要翻译：提供了一种通过从存储器件频率运行完全异步的存储器通道来减少延迟的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从外部存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。第一个工作频率是存储器通道的最大设计工作频率，第一个工作频率与第二个工作频率无关。

23. 发明申请

US20090190429A1 System to Provide Memory System Power Reduction Without Reducing Overall Memory System Performance 失效
标题翻译：系统提供内存系统功耗而不降低整体内存系统性能
公开(公告)号：US20090190429A1
公开(公告)日：2009-07-30
申请号：US12018952
申请日：2008-01-24
申请人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
发明人： Mark A. Brittain , Kevin C. Gower , Warren E. Maule
IPC分类号： G11C8/18
CPC分类号： G11C5/04 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F13/4243 , G11C8/18 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/159
摘要： A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices.
摘要翻译：提供了一种提供存储器系统功率降低而不降低整体存储器系统性能的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备。存储器集线器设备包括命令队列，其经由存储器通道以第一工作频率从存储器控制器接收存储器访问命令。存储器系统还包括集成在存储器集线器设备中的存储器集线器控制器。存储器集线器控制器以第二工作频率从命令队列读取存储器访问命令。通过以第一工作频率接收存储器访问命令并且以第二工作频率读取存储器访问命令，实现异步边界。使用异步边界，存储器通道以最大设计的工作带宽工作，而第二工作频率被独立地降低以减少由该组存储器件消耗的功率。

24. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

25. 发明授权

US07512762B2 System, method and storage medium for a memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的存储器子系统的系统，方法和存储介质
公开(公告)号：US07512762B2
公开(公告)日：2009-03-31
申请号：US10977038
申请日：2004-10-29
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.
摘要翻译：具有位置读数据延迟的存储器子系统，其包括具有一个或多个存储器模块的级联互连系统，存储器控制器和一个或多个存储器总线。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过分组化的多传输接口经由存储器总线互连。

26. 发明申请

US20090063922A1 System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module 失效
标题翻译：用于在存储器模块的存储器集线器设备中执行纠错操作的系统
公开(公告)号：US20090063922A1
公开(公告)日：2009-03-05
申请号：US11848349
申请日：2007-08-31
申请人： Kevin C. Gower , Warren E. Maule
发明人： Kevin C. Gower , Warren E. Maule
IPC分类号： G06F11/00
CPC分类号： G06F11/1008
摘要： A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises error correction logic integrated in the memory hub device and coupled to the link interface. The error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.
摘要翻译：提供了一种用于在存储器模块中执行纠错操作的存储器系统。存储器系统包括集成在存储器模块中的存储器集线器设备和耦合到存储器集线器设备的一组存储器设备。存储器集线器设备包括集成到存储器集线器设备中的链路接口，其提供外部存储器控制器和该组存储器设备之间的通信路径。存储器集线器设备还包括集成在存储器集线器设备中并耦合到链路接口的纠错逻辑。误差校正逻辑对在链路接口和存储器件组之间传送的数据执行纠错操作。存储器集线器件通过外部存储器控制器和链路接口之间的存储器通道发送和接收数据，而没有任何纠错码。

27. 发明申请

US20080005496A1 Memory Systems for Automated Computing Machinery 有权
标题翻译：自动计算机存储系统
公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
申请人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Daniel M. Dreps , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译：公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。

28. 发明授权

US5328233A Combination child's seat and armrest for a vehicle 失效
标题翻译：组合儿童座椅和扶手用于车辆
公开(公告)号：US5328233A
公开(公告)日：1994-07-12
申请号：US970968
申请日：1992-11-03
申请人： Warren E. Maule
发明人： Warren E. Maule
IPC分类号： B60N2/06 , B60N2/30 , B60N2/34 , B60N2/75 , A47C13/00
CPC分类号： B60N2/062 , B60N2/06 , B60N2/3081 , B60N2/345 , B60N2/4673 , B60N2/468
摘要： A combination child's seat and armrest assembly includes an upper portion and a lower portion. The portions are pivotably attached to each other at the front of the assembly, thereby providing for the raising and lowering of the upper portion. In its lowered position, the assembly functions as an armrest for the driver and passenger. In its raised position, a child may be seated facing front, or the bottom side of the raised upper portion. This positioning securely fits the child between the raised upper portion and the seat back of the vehicle's seat. A bed telescoping between the rear seat and the front seat may also be provided.
摘要翻译：组合儿童座椅和扶手组件包括上部和下部。这些部分在组件的前部可枢转地彼此附接，从而提供上部的升高和降低。在其降低的位置，组件用作驾驶员和乘客的扶手。在其抬起的位置，一个孩子可以面向前部或者凸起的上部的底侧。该定位将孩子牢固地适配在车辆座椅的凸起的上部和座椅靠背之间。还可以设置在后座椅和前座椅之间伸缩的床。

29. 发明授权

US08245105B2 Cascade interconnect memory system with enhanced reliability 有权
标题翻译：级联互连存储器系统具有增强的可靠性
公开(公告)号：US08245105B2
公开(公告)日：2012-08-14
申请号：US12166235
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.
摘要翻译：一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。

30. 发明申请

US20120151171A1 PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权
标题翻译：在具有INDETERMINATE读取数据延迟的存储器系统中提供帧起始指示
公开(公告)号：US20120151171A1
公开(公告)日：2012-06-14
申请号：US13397819
申请日：2012-02-16
申请人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Warren E. Maule , Robert B. Tremaine
IPC分类号： G06F12/00
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator.
摘要翻译：具有不确定的读取数据延迟的存储器系统，其包括存储器控制器和一个或多个集线器设备。存储器控制器被配置为经由上游信道接收数据传输，并且通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。数据帧包括由存储器控制器用于将数据帧与由存储器控制器发出的相应读取指令相关联的识别标签。一个或多个集线器设备经由上游信道和下游信道以级联互连方式与存储器控制器通信。每个集线器设备被配置用于经由上游信道或下游信道接收数据传输，并且用于通过检测帧起始指示符来确定数据传输的全部或一个子集是否包括数据帧。

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