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21. 发明授权

US08634239B2 Hybrid multi-level cell programming sequences 有权
标题翻译：混合多级单元编程序列
公开(公告)号：US08634239B2
公开(公告)日：2014-01-21
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

22. 发明申请

US20130170293A1 HYBRID MULTI-LEVEL CELL PROGRAMMING SEQUENCES 有权
标题翻译：混合多级细胞编程序列
公开(公告)号：US20130170293A1
公开(公告)日：2013-07-04
申请号：US13339017
申请日：2011-12-28
申请人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
发明人： Steven Sprouse , Chris Avila , Sergey Anatolievich Gorobets
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory device implements hybrid programming sequences for writing data to multiple level cells (MLCs). The memory device obtains specified data to write to the MLC and selects among multiple different programming techniques to write the specified data. Each of the programming techniques establishes a charge configuration in the MLC that represents multiple data bits. The memory device writes the specified data to the MLC using the selected programming technique. In one implementation, the programming techniques include a robust programming technique that preserves previously written data in the MLC in the event of a write abort of the specified data and an additional programming technique that has higher average performance than the robust programming technique. The selection may be made based on a wide variety of criteria, including whether data has been previously written to a block that includes the MLC.
摘要翻译：存储器件实现用于将数据写入多级单元（MLC）的混合编程序列。存储器件获得指定的数据以写入MLC，并在多种不同的编程技术之间进行选择来写入指定的数据。每个编程技术在MLC中建立代表多个数据位的电荷配置。存储器件使用所选的编程技术将指定的数据写入MLC。在一个实现中，编程技术包括鲁棒编程技术，其在写入中止指定数据的情况下保留MLC中的先前写入的数据，以及具有比鲁棒编程技术更高的平均性能的附加编程技术。可以基于各种各样的标准来进行选择，包括数据是否已经被预先写入包括MLC的块。

23. 发明授权

US08001304B2 Portable memory device with multiple I/O interfaces wherein each I/O interface has respective protocol and device parameters are requested from one I/O interface using only respective protocol 有权
标题翻译：具有多个I / O接口的便携式存储器件，其中每个I / O接口具有相应的协议和设备参数，仅使用相应协议从一个I / O接口请求
公开(公告)号：US08001304B2
公开(公告)日：2011-08-16
申请号：US12032501
申请日：2008-02-15
申请人： Ka Ian Yung , Steven Sprouse , Dhaval Parikh , Nathan Rapaport
发明人： Ka Ian Yung , Steven Sprouse , Dhaval Parikh , Nathan Rapaport
IPC分类号： G06F13/12 , G06F3/00 , G06F12/00 , H01R25/00 , G06F1/16
CPC分类号： G06F13/385
摘要： A non-volatile storage device has first and second controllers that provide external access to non-volatile memory using different protocols. In response to a request from the first controller, the second controller retrieves parameters from the non-volatile memory and provides the retrieved parameters to the first controller. In one embodiment, the device parameters are USB descriptors, which may include a vendor ID, a product ID, a product string, and/or a serial number. The first controller may be a Universal Serial Bus (USB) card reader controller. Examples of the second controller include a Secure Digital (SD) controller, a CompactFlash (CF) controller, a MemoryStick controller, or a different type of controller that is able to provide external access to the non-volatile memory. The first controller provides the device parameters to a host during enumeration of the non-volatile storage device. The device parameters may be used to establish settings for the first controller.
摘要翻译：非易失性存储设备具有使用不同协议提供对非易失性存储器的外部访问的第一和第二控制器。响应于来自第一控制器的请求，第二控制器从非易失性存储器检索参数，并将所检索的参数提供给第一控制器。在一个实施例中，设备参数是USB描述符，其可以包括供应商ID，产品ID，产品串和/或序列号。第一控制器可以是通用串行总线（USB）读卡器控制器。第二控制器的示例包括安全数字（SD）控制器，CompactFlash（CF）控制器，MemoryStick控制器或能够提供对非易失性存储器的外部访问的不同类型的控制器。第一控制器在枚举非易失性存储设备期间向主机提供设备参数。设备参数可用于建立第一控制器的设置。

24. 发明授权

US09063862B2 Expandable data cache 有权
标题翻译：可扩展数据缓存
公开(公告)号：US09063862B2
公开(公告)日：2015-06-23
申请号：US13109777
申请日：2011-05-17
申请人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
发明人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0871 , G06F12/0897 , G06F2212/2022 , G06F2212/214 , G06F2212/2515 , G06F2212/466 , G06F2212/6012
摘要： A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.
摘要翻译：公开了一种用于存储设备中的高速缓存管理的方法和系统。存储设备中的未使用的存储器的一部分用于临时数据高速缓存，使得可以使用两级缓存（诸如永久数据高速缓存和临时数据高速缓存）。存储设备可以管理临时数据高速缓存，以便在临时数据高速缓存中保持干净的条目。以这种方式，与临时数据高速缓存相关联的存储区域可以立即回收并重新筛选以用于不同的目的，而不需要无关的复制操作。

25. 发明授权

US08947883B2 Low profile wire bonded USB device 有权
标题翻译：薄型线焊接USB设备
公开(公告)号：US08947883B2
公开(公告)日：2015-02-03
申请号：US11965691
申请日：2007-12-27
申请人： Suresh Upadhyayula , Robert C. Miller , Hem Takiar , Steven Sprouse , Ka Ian Yung
发明人： Suresh Upadhyayula , Robert C. Miller , Hem Takiar , Steven Sprouse , Ka Ian Yung
IPC分类号： H05K7/00 , G06K19/077 , H01L23/00
CPC分类号： H01L21/02 , G06K19/07732 , G06K19/07735 , G06K19/07743 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/48091 , H01L2224/49171 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , Y10T29/41 , Y10T29/49117 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A low profile USB flash memory device, and methods of forming same, are disclosed. The USB flash memory device includes an integrated circuit memory portion and a USB connector. The memory portion and the USB connector may be integrally formed on the same substrate. The USB flash memory device includes a substrate on which is mounted one or more flash memory die, a controller die, passive components and an LED for indicating when the memory is being accessed. In contrast to prior art USB memory devices which used TSOP packages mounted on a printed circuit board, the semiconductor die of the present invention are affixed to the substrate and wire bonded in a SIP configuration. Omitting the encapsulated TSOP packages allows a reduction in the overall thickness of the USB flash memory device.
摘要翻译：公开了一种低调USB闪存设备及其形成方法。 USB闪存设备包括集成电路存储器部分和USB连接器。存储器部分和USB连接器可以整体地形成在同一基板上。 USB闪存设备包括一个基板，在该基板上安装有一个或多个闪存芯片，控制器芯片，无源元件和LED，用于指示何时访问存储器。与使用安装在印刷电路板上的TSOP封装的现有技术的USB存储器装置相比，本发明的半导体管芯被固定到衬底上并以SIP构造接合。省略封装的TSOP封装允许减少USB闪存设备的总体厚度。

26. 发明授权

US08468294B2 Non-volatile memory with multi-gear control using on-chip folding of data 有权
标题翻译：具有多档位控制的非易失性存储使用片上数据折叠
公开(公告)号：US08468294B2
公开(公告)日：2013-06-18
申请号：US12642611
申请日：2009-12-18
申请人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
发明人： Jianmin Huang , Chris Avila , Lee M. Gavens , Steven Sprouse , Sergey Anatolievich Gorobets , Neil David Hutchinson
IPC分类号： G06F3/06 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

27. 发明申请

US20120297140A1 EXPANDABLE DATA CACHE 有权
标题翻译：可扩展数据缓存
公开(公告)号：US20120297140A1
公开(公告)日：2012-11-22
申请号：US13109777
申请日：2011-05-17
申请人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
发明人： William Wu , Sergey Anatolievich Gorobets , Steven Sprouse , Alan Bennett
IPC分类号： G06F12/12
CPC分类号： G06F12/0871 , G06F12/0897 , G06F2212/2022 , G06F2212/214 , G06F2212/2515 , G06F2212/466 , G06F2212/6012
摘要： A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations.
摘要翻译：公开了一种用于存储设备中的高速缓存管理的方法和系统。存储设备中的未使用的存储器的一部分用于临时数据高速缓存，使得可以使用两级缓存（诸如永久数据高速缓存和临时数据高速缓存）。存储设备可以管理临时数据高速缓存，以便在临时数据高速缓存中保持干净的条目。以这种方式，与临时数据高速缓存相关联的存储区域可以立即回收并重新筛选以用于不同的目的，而不需要无关的复制操作。

28. 发明申请

US20110153911A1 METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING 有权
标题翻译：通过块交互实现平行排列的方法和系统
公开(公告)号：US20110153911A1
公开(公告)日：2011-06-23
申请号：US12642181
申请日：2009-12-18
申请人： Steven Sprouse , Chris Avila , Jianmin Huang
发明人： Steven Sprouse , Chris Avila , Jianmin Huang
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G11C11/5628 , G06F12/0246 , G06F12/0851 , G06F12/0871 , G06F2212/2022 , G06F2212/214 , G06F2212/222 , G06F2212/284 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G11C7/1042 , G11C16/0483 , G11C2207/2245 , G11C2211/5641 , G11C2211/5643
摘要： A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die.
摘要翻译：通过块交织实现管芯并行的方法和系统包括具有多个非易失性存储器管芯的非易失性存储器，其中每个管芯具有缓存存储区域和主存储区域。控制器被配置为接收数据并将顺序寻址的数据写入到第一管芯的缓存存储区域。控制器在将顺序寻址的数据写入与第一管芯的主存储区域的块相等的第一管芯的高速缓存存储区域之后，将附加数据写入下一个管芯的高速缓存存储区域，直到顺序寻址的数据被写入下一个芯片的高速缓存区域等于主存储区域的块。高速缓存存储区域可以被复制到第一裸片上的主存储区域，而缓存存储区域被写入到下一个芯片上。

29. 发明申请

US20110010484A1 OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY 有权
标题翻译：优化的非易失性存储器页面编程订单
公开(公告)号：US20110010484A1
公开(公告)日：2011-01-13
申请号：US12499219
申请日：2009-07-08
申请人： Steven Sprouse , Jianmin Huang , Chris Avila , Yichao Huang , Emilio Yero
发明人： Steven Sprouse , Jianmin Huang , Chris Avila , Yichao Huang , Emilio Yero
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C11/5628 , G11C2211/5648
摘要： During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.
摘要翻译：在非易失性存储系统中的编程数据传输过程中，数据的记录单元从主机传送到诸如存储卡的存储设备。对于每个记录单元，数据页按照这样的顺序排列，使得在写入时间较少的页面之前提供需要更长时间写入存储器件的存储器阵列的页面。由于发生更大程度的并行处理，记录单元的整体编程时间减少。当将编程所需的时间更长的页面编程到存储器阵列时，将编程所需的较少时间的页面传送到存储器件。编程完成后，存储器信号通知主机传送下一个记录单元。数据页可以包括下页，中页和上页。

30. 发明申请

US20090307389A1 SWITCHABLE ACCESS STATES FOR NON-VOLATILE STORAGE DEVICES 审中-公开
标题翻译：非易失存储设备的可切换访问状态
公开(公告)号：US20090307389A1
公开(公告)日：2009-12-10
申请号：US12136672
申请日：2008-06-10
申请人： Steven Sprouse , Henry Hutton , Dhaval Parikh
发明人： Steven Sprouse , Henry Hutton , Dhaval Parikh
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Techniques for switching access states for accessing non-volatile are disclosed. A plurality of non-volatile memory portions can be effectively presented as: (a) a single logical unit in a first access state (“single unit access state”) and (b) as multiple logical units in a second access state (“multi-unit access state”). An access switching system can be provided for a device that includes a plurality of non-volatile storage portions. As a result, the device can be operable to effectively switch between the first and second access states. In the first access state, the plurality of non-volatile storage portions can be effectively presented as a single logical unit for access by another device, thereby allowing the other device to effectively access the plurality of non-volatile storage portions from a single access point. However, the device can also be operable to switch to a second access state in which the plurality of the non-volatile storage portions can be effectively presented to the other device as multiple logical units, thereby allowing the other device to access the plurality of non-volatile storage portions individually by using multiple access points respectively associated with the multiple logical units presented to the other device.
摘要翻译：公开了用于切换访问非易失性的访问状态的技术。可以有效地呈现多个非易失性存储器部分：（a）处于第一访问状态（“单个单元访问状态”）中的单个逻辑单元和（b）作为第二访问状态中的多个逻辑单元（“多个” -unit访问状态“）。可以为包括多个非易失性存储部分的装置提供接入交换系统。结果，该设备可操作以有效地在第一和第二访问状态之间切换。在第一访问状态下，可以将多个非易失性存储部分有效地呈现为单个逻辑单元以供另一设备访问，从而允许其他设备从单个访问点有效地访问多个非易失性存储部分。然而，该设备还可以用于切换到第二访问状态，其中多个非易失性存储部分可以被有效地呈现给另一设备作为多个逻辑单元，从而允许其他设备访问多个非易失性存储部分通过使用分别与呈现给另一个设备的多个逻辑单元相关联的多个接入点来单独地分配非易失性存储部分。

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