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    • 22. 发明授权
    • Wafer level packaged focal plane array
    • 晶圆级封装焦平面阵列
    • US08608894B2
    • 2013-12-17
    • US13298955
    • 2011-11-17
    • Stephen H. BlackThomas A. Kocian
    • Stephen H. BlackThomas A. Kocian
    • G01J1/04
    • H01L27/14683H01L27/14618H01L27/14649H01L2924/0002H01L2924/00
    • A method for manufacturing a wafer level packaged focal plane array, in accordance with certain embodiments, includes forming a detector wafer, which may include forming detector arrays and read-out circuits. The method may also include forming a lid wafer. Forming the lid wafer may include polishing a surface of a magnetically confined Czochralski (MCZ) wafer, bonding a Czochralski wafer to the MCZ wafer, and forming pockets in the Czochralski wafer. Each pocked may expose a portion of the polished surface of the MCZ wafer. The method may further include bonding the lid wafer and the detector wafer together such that the each detector array and read-out circuit are sealed within a different pocket, thereby forming a plurality of wafer level packaged focal plane arrays. The method may additionally include separating at least one wafer level packaged focal plan array from the plurality of wafer level packaged focal plane arrays.
    • 根据某些实施例的用于制造晶片级封装焦平面阵列的方法包括形成检测器晶片,其可以包括形成检测器阵列和读出电路。 该方法还可以包括形成盖子晶片。 形成盖晶片可以包括抛光限磁切克劳斯基(MCZ)晶片的表面,将切克劳斯基晶片结合到MCZ晶片,以及在切克劳斯基晶片中形成凹坑。 每一个可能会暴露MCZ晶片抛光表面的一部分。 该方法还可以包括将盖晶片和检测器晶片结合在一起,使得每个检测器阵列和读出电路被密封在不同的口袋内,由此形成多个晶片级封装的焦平面阵列。 该方法可以另外包括从多个晶片级封装焦平面阵列分离至少一个晶片级封装焦点平面图阵列。
    • 25. 发明授权
    • Near complete charge transfer device
    • 近完全电荷转移装置
    • US6133596A
    • 2000-10-17
    • US296047
    • 1999-04-21
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • H01L27/146H01L29/768H01L27/148
    • H01L27/146H01L29/768
    • A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port. A clock signal (P1) applied to the gate of D1 and a clock signal (P3) applied to the gate of D3 are each predetermined to deplete an underlying surface region of the substrate for forming the first primary charge storage well and the second primary charge storage well, respectively, without requiring the use of diffusion implants as in conventional bucket brigade devices.
    • 电荷转移结构(30)包括由半导体材料构成的衬底,并且耦合到衬底的表面,每个具有栅极端子的多个串联耦合器件。 多个串联耦合器件包括限定第一初级电荷存储阱的第一单端口器件(D1),限定第二电荷存储阱的第二单端口器件(D3),限定第一电荷存储阱 传输设备,定义第二传送设备的第二双端口设备(D4)和每个定义共享共享设备(CD)的第三双端口设备的两个实例。 这些器件的端口以D1,D2,CD,D3,D4,CD给出的顺序串联在一起,用于在第一和第二主要电荷存储阱之间传送电荷。 通过用作输入端口和输出端口的单个扩散器将电荷插入并从每个第一和第二主电荷存储阱中抽出。 施加到D1的栅极的时钟信号(P1)和施加到D3的栅极的时钟信号(P3)都被预先设定,以消耗用于形成第一初级电荷存储阱的基板的下表面区域和第二主要电荷 存储井,而不需要使用扩散植入物,如在常规斗式装置中。
    • 30. 发明授权
    • Differential current mode output circuit for electro-optical sensor arrays
    • 差分电流模式输出电路用于电光传感器阵列
    • US06344651B1
    • 2002-02-05
    • US09427645
    • 1999-10-27
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • James T. WoolawayWilliam J. ParrishStephen H. Black
    • H03F345
    • G01J5/24H03F3/082H03F3/45197H03F3/68H03F2203/45652H03F2203/45658H03F2203/45682H04N5/33
    • A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node. The current flow through Rs is proportional to a difference between Vs and Vr, and is thus indicative of a magnitude of Vs.
    • 差分电流模式放大器电路(5,5')包括具有第一电流源的第一电路支路,该第一电流源提供与第一电路节点(n1)上的第一晶体管(m1)串联耦合的电流I1。 第一晶体管具有用于耦合到输入信号电位(Vs)的控制端子。 Vs是从放射线检测器阵列的单位单元获得的,并且表示积分的光子诱导电荷的大小。 第一电路支路输出第一输出电流(Is)。 第二电路支路包括提供与第二电路节点(n2)上的第二晶体管(m2)串联耦合的电流I2的第二电流源。 第二晶体管具有用于耦合到输入参考电位(Vr)的控制端子。 第二电路支路输出第二输出电流(Ir)。 电阻(Rs)在第一电路节点和第二节点处耦合在第一电路支路和第二电路支路之间。 通过Rs的电流与Vs和Vr之间的差成比例,因此表示Vs的大小。