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    • 4. 发明授权
    • Wafer level packaged focal plane array
    • 晶圆级封装焦平面阵列
    • US08608894B2
    • 2013-12-17
    • US13298955
    • 2011-11-17
    • Stephen H. BlackThomas A. Kocian
    • Stephen H. BlackThomas A. Kocian
    • G01J1/04
    • H01L27/14683H01L27/14618H01L27/14649H01L2924/0002H01L2924/00
    • A method for manufacturing a wafer level packaged focal plane array, in accordance with certain embodiments, includes forming a detector wafer, which may include forming detector arrays and read-out circuits. The method may also include forming a lid wafer. Forming the lid wafer may include polishing a surface of a magnetically confined Czochralski (MCZ) wafer, bonding a Czochralski wafer to the MCZ wafer, and forming pockets in the Czochralski wafer. Each pocked may expose a portion of the polished surface of the MCZ wafer. The method may further include bonding the lid wafer and the detector wafer together such that the each detector array and read-out circuit are sealed within a different pocket, thereby forming a plurality of wafer level packaged focal plane arrays. The method may additionally include separating at least one wafer level packaged focal plan array from the plurality of wafer level packaged focal plane arrays.
    • 根据某些实施例的用于制造晶片级封装焦平面阵列的方法包括形成检测器晶片,其可以包括形成检测器阵列和读出电路。 该方法还可以包括形成盖子晶片。 形成盖晶片可以包括抛光限磁切克劳斯基(MCZ)晶片的表面,将切克劳斯基晶片结合到MCZ晶片,以及在切克劳斯基晶片中形成凹坑。 每一个可能会暴露MCZ晶片抛光表面的一部分。 该方法还可以包括将盖晶片和检测器晶片结合在一起,使得每个检测器阵列和读出电路被密封在不同的口袋内,由此形成多个晶片级封装的焦平面阵列。 该方法可以另外包括从多个晶片级封装焦平面阵列分离至少一个晶片级封装焦点平面图阵列。
    • 6. 发明申请
    • Wafer Level Packaged Focal Plane Array
    • 晶圆级封装焦平面阵列
    • US20120139072A1
    • 2012-06-07
    • US13298955
    • 2011-11-17
    • Stephen H. BlackThomas A. Kocian
    • Stephen H. BlackThomas A. Kocian
    • H01L31/02H01L31/0232
    • H01L27/14683H01L27/14618H01L27/14649H01L2924/0002H01L2924/00
    • A method for manufacturing a wafer level packaged focal plane array, in accordance with certain embodiments, includes forming a detector wafer, which may include forming detector arrays and read-out circuits. The method may also include forming a lid wafer. Forming the lid wafer may include polishing a surface of a magnetically confined Czochralski (MCZ) wafer, bonding a Czochralski wafer to the MCZ wafer, and forming pockets in the Czochralski wafer. Each pocked may expose a portion of the polished surface of the MCZ wafer. The method may further include bonding the lid wafer and the detector wafer together such that the each detector array and read-out circuit are sealed within a different pocket, thereby forming a plurality of wafer level packaged focal plane arrays. The method may additionally include separating at least one wafer level packaged focal plan array from the plurality of wafer level packaged focal plane arrays.
    • 根据某些实施例的用于制造晶片级封装焦平面阵列的方法包括形成检测器晶片,其可以包括形成检测器阵列和读出电路。 该方法还可以包括形成盖子晶片。 形成盖晶片可以包括抛光限磁切克劳斯基(MCZ)晶片的表面,将切克劳斯基晶片结合到MCZ晶片,以及在切克劳斯基晶片中形成凹坑。 每一个可能会暴露MCZ晶片抛光表面的一部分。 该方法还可以包括将盖晶片和检测器晶片结合在一起,使得每个检测器阵列和读出电路被密封在不同的口袋内,由此形成多个晶片级封装的焦平面阵列。 该方法可以另外包括从多个晶片级封装焦平面阵列分离至少一个晶片级封装焦点平面图阵列。
    • 7. 发明授权
    • Electro-optical package with drop-in aperture
    • 电光封装带有光圈
    • US06762868B2
    • 2004-07-13
    • US09990952
    • 2001-11-09
    • Jwei Wien LiuThomas A. Kocian
    • Jwei Wien LiuThomas A. Kocian
    • G02B2600
    • B81B7/0067H01L23/552H01L2924/0002H01L2924/00
    • A drop-in aperture 20, which improves the performance and lowers the cost of electro-optical SLM packages. The disclosed package provides a separate metal light shield (aperture) 20 and antireflective coated cover 33, and positions the aperture 20 inside the package 40 in close proximity to the SLM's 41 surface. This approach further uses an on-chip SLM light shield to define the projected screen border, thereby making the edge definition of the metal drop-in aperture less critical. Therefore, the cover can be mounted well away from the plane of the SLM, which relaxes the defect requirements of the cover and lowers the cost of the overall package. The package of this invention improves the performance and lifetime and lowers the cost of projection display systems.
    • 插入孔20,其提高了性能并降低了电光SLM封装的成本。 所公开的封装提供单独的金属光屏蔽(孔)20和防反射涂层盖33,并且将孔20定位在封装40内靠近SLM的41表面。 该方法还使用片上SLM光罩来定义投影屏幕边界,从而使得金属入射孔的边缘定义不太关键。 因此,盖可以远离SLM的平面安装,这放宽了盖的缺陷要求并降低了整体封装的成本。 本发明的封装提高了性能和使用寿命并降低了投影显示系统的成本。