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21. 发明授权

US08569868B2 Device having and method for forming fins with multiple widths 有权
标题翻译：具有用于形成多个宽度的翅片的装置和方法
公开(公告)号：US08569868B2
公开(公告)日：2013-10-29
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

22. 发明申请

US20130207270A1 DUAL-METAL SELF-ALIGNED WIRES AND VIAS 有权
标题翻译：双金属自对准线和VIAS
公开(公告)号：US20130207270A1
公开(公告)日：2013-08-15
申请号：US13371493
申请日：2012-02-13
申请人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/49
CPC分类号： H01L23/485 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features.
摘要翻译：形成半导体结构的方法，包括在半导体衬底上形成第一导电间隔物; 相对于所述第一导电间隔物形成第二导电间隔物，所述第二导电间隔物中的至少一个与所述第一导电间隔物中的每一个相邻并与之接触以形成组合的导电间隔物; 相对于第一导电间隔物使第二导电间隔物凹陷，使得第一导电间隔物延伸超过第二导电间隔物; 沉积ILD以覆盖除了第一导电间隔物的暴露边缘之外的第一和第二间隔物; 图案化第一导电间隔物的暴露边缘以将预定位置中的第一导电间隔物的边缘凹入以形成相对于ILD的凹部; 并用绝缘材料填充凹槽，以将第一导电间隔物的未加工的边缘作为过孔留下以后的布线特征。

23. 发明申请

US20120280365A1 DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS 有权
标题翻译：具有形成具有多个宽度的FINS的装置和方法
公开(公告)号：US20120280365A1
公开(公告)日：2012-11-08
申请号：US13552296
申请日：2012-07-18
申请人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Steven J. Holmes , Xuefeng Hua , Ying Zhang
IPC分类号： H01L29/06
CPC分类号： H01L21/308 , H01L21/033 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.
摘要翻译：公开了一种用于半导体器件的结构。该结构包括第一特征和第二特征。第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

24. 发明申请

US20120241913A1 MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT 有权
标题翻译：具有可移除边缘延伸元件的微电子基板
公开(公告)号：US20120241913A1
公开(公告)日：2012-09-27
申请号：US13490239
申请日：2012-06-06
申请人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
发明人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
IPC分类号： H01L29/06
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译：提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。前表面是物品的主要表面。具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦，周缘连接到内边缘。

25. 发明申请

US20120181613A1 Methods for Forming Field Effect Transistor Devices With Protective Spacers 审中-公开
标题翻译：用保护隔离层形成场效应晶体管器件的方法
公开(公告)号：US20120181613A1
公开(公告)日：2012-07-19
申请号：US13009271
申请日：2011-01-19
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823418 , H01L21/823468 , H01L29/78
摘要： A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.
摘要翻译：一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。

26. 发明申请

US20120142182A1 MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
标题翻译：通过选择性沉积的微电子结构
公开(公告)号：US20120142182A1
公开(公告)日：2012-06-07
申请号：US13372058
申请日：2012-02-13
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/28
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖半导体鳍片可以使用侧向生长方法制造其它微电子结构。

27. 发明申请

US20120126358A1 TONE INVERSION WITH PARTIAL UNDERLAYER ETCH 失效
标题翻译：带有部分底层蚀刻的色调
公开(公告)号：US20120126358A1
公开(公告)日：2012-05-24
申请号：US12952248
申请日：2010-11-23
申请人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
发明人： John C. Arnold , Sean D. Burns , Matthew E. Colburn , Steven J. Holmes , Yunpeng Yin
IPC分类号： H01L21/311 , H01L23/00 , H01L21/768
CPC分类号： H01L23/00 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
摘要翻译：用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

28. 发明申请

US20110204523A1 METHOD OF FABRICATING DUAL DAMASCENE STRUCTURES USING A MULTILEVEL MULTIPLE EXPOSURE PATTERNING SCHEME 有权
标题翻译：使用多次多次曝光方案制作双重结构结构的方法
公开(公告)号：US20110204523A1
公开(公告)日：2011-08-25
申请号：US12708877
申请日：2010-02-19
申请人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
发明人： John C. Arnold , Kuang-Jung Chen , Matthew E. Colburn , Dario L. Goldfarb , Stefan Harrer , Steven J. Holmes , Pushkara Varanasi
IPC分类号： H01L23/522 , G03F7/20
CPC分类号： H01L23/53295 , G03F7/091 , G03F7/38 , H01L21/0274 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.
摘要翻译：一种用于制造双镶嵌结构的方法包括提供涂覆在下面的电介质堆叠上的第一光致抗蚀剂层，将所述第一光致抗蚀剂层暴露于第一预定图案的光，将第二光致抗蚀剂层涂覆到预曝光的第一光致抗蚀剂层上，第二光致抗蚀剂层到第二预定图案的光，任选地后曝光烘烤多层光致抗蚀剂层并显影所述光致抗蚀剂层以在光致抗蚀剂层中形成多层双镶嵌结构。

29. 发明申请

US20110049680A1 DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS 有权
标题翻译：双重接触跟踪只能分离分离过程
公开(公告)号：US20110049680A1
公开(公告)日：2011-03-03
申请号：US12551801
申请日：2009-09-01
申请人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
发明人： Sean D. Burns , Matthew E. Colburn , Steven J. Holmes
IPC分类号： H01L29/06 , G03F7/20 , H01L21/461
CPC分类号： H01L21/31144 , G03F7/0035 , H01L21/0271 , H01L21/0338
摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.
摘要翻译：集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。

30. 发明授权

US07883829B2 Lithography for pitch reduction 有权
标题翻译：减光平版印刷
公开(公告)号：US07883829B2
公开(公告)日：2011-02-08
申请号：US12184438
申请日：2008-08-01
申请人： Steven J. Holmes , Xuefeng Hua , Willard E. Conley
发明人： Steven J. Holmes , Xuefeng Hua , Willard E. Conley
IPC分类号： G03F7/00 , G03F7/20 , G03F7/40
CPC分类号： H01L21/0337 , H01L21/0338
摘要： In one embodiment, a photoresist is lithographically patterned to form an array of patterned photoresist portions having a pitch near twice a minimum feature size. Fluorine-containing polymer spacers are formed on sidewalls of the patterned photoresist portions. The pattern of the fluorine-containing polymer spacers is transferred into an underlying layer to form a pattern having a sublithographic pitch. In another embodiment, a first pattern in a first photoresist is transferred into a first ARC layer underneath to form first ARC portions. A planarizing second optically dense layer, a second ARC layer, and a second photoresist are applied over the first ARC portions. A second pattern in the second photoresist is transferred into the second ARC layer to form second ARC portions. The combination of the first ARC portions and second ARC portions function as an etch mask to pattern an underlying layer with a composite pattern having a sublithographic pitch.
摘要翻译：在一个实施例中，光刻胶被图案化以形成具有接近两倍最小特征尺寸的间距的图案化光致抗蚀剂部分的阵列。含氟聚合物间隔物形成在图案化的光致抗蚀剂部分的侧壁上。将含氟聚合物间隔物的图案转移到下层中以形成具有亚光刻间距的图案。在另一个实施例中，将第一光致抗蚀剂中的第一图案转移到下面的第一ARC层中以形成第一ARC部分。在第一ARC部分上施加平坦化的第二光致密层，第二ARC层和第二光致抗蚀剂。将第二光致抗蚀剂中的第二图案转移到第二ARC层中以形成第二ARC部分。第一ARC部分和第二ARC部分的组合用作蚀刻掩模，以用具有亚光刻间距的复合图案来图案化下面的层。

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