会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • TONE INVERSION WITH PARTIAL UNDERLAYER ETCH
    • 带有部分底层蚀刻的色调
    • US20120126358A1
    • 2012-05-24
    • US12952248
    • 2010-11-23
    • John C. ArnoldSean D. BurnsMatthew E. ColburnSteven J. HolmesYunpeng Yin
    • John C. ArnoldSean D. BurnsMatthew E. ColburnSteven J. HolmesYunpeng Yin
    • H01L21/311H01L23/00H01L21/768
    • H01L23/00H01L21/0337H01L21/31144H01L21/76816H01L2924/0002H01L2924/00
    • A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
    • 用于集成电路制造的色调反转的方法包括:在衬底的顶部上提供具有底层的衬底; 产生第一图案,所述第一图案被部分地蚀刻到所述底层的一部分中,使得所述底层的剩余部分被保护并形成第二图案,并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料(IRM)覆盖第一个图案; 并将第二图案刻蚀成衬底。 用于集成电路制造的色调反转的结构包括:衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案,所述第一图案被部分地蚀刻到所述底层的一部分中,使得所述底层的剩余部分被保护并形成第二图案,并且使得所述第一图案不暴露 底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料(IRM)层。
    • 2. 发明授权
    • Tone inversion with partial underlayer etch for semiconductor device formation
    • 用于半导体器件形成的部分底层蚀刻的色调反演
    • US08470711B2
    • 2013-06-25
    • US12952248
    • 2010-11-23
    • John C. ArnoldSean D. BurnsMatthew E. ColburnSteven J. HolmesYunpeng Yin
    • John C. ArnoldSean D. BurnsMatthew E. ColburnSteven J. HolmesYunpeng Yin
    • H01L21/44
    • H01L23/00H01L21/0337H01L21/31144H01L21/76816H01L2924/0002H01L2924/00
    • A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.
    • 用于集成电路制造的色调反转的方法包括:在衬底的顶部上提供具有底层的衬底; 产生第一图案,所述第一图案被部分地蚀刻到所述底层的一部分中,使得所述底层的剩余部分被保护并形成第二图案,并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料(IRM)覆盖第一个图案; 并将第二图案刻蚀成衬底。 用于集成电路制造的色调反转的结构包括:衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案,所述第一图案被部分蚀刻到所述底层的一部分中,使得所述底层的剩余部分被保护并形成第二图案,并且使得所述第一图案不暴露 底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料(IRM)层。
    • 4. 发明授权
    • Mask and etch process for pattern assembly
    • 掩模和蚀刻工艺用于图案组装
    • US08119531B1
    • 2012-02-21
    • US13013935
    • 2011-01-26
    • John C. ArnoldSean D. BurnsMatthew E. ColburnYunpeng Yin
    • John C. ArnoldSean D. BurnsMatthew E. ColburnYunpeng Yin
    • H01L21/311
    • H01L21/0337H01L21/0331
    • A method of forming a trench is provided that includes providing a stack having a semiconductor layer or dielectric layer, a metal nitride layer, a leveling layer, and a first mask layer. First trenches are etched through the first mask layer and the leveling layer. The first mask layer is removed. A second mask layer is formed on the leveling layer. Second trenches are formed through the second mask layer, wherein the base of the second trenches do not extend through the metal nitride layer. The second mask layer is removed. Exposed portions of the metal nitride layer are etched selectively to the semiconductor layer and remaining portions of the leveling layer to extend the first trenches and the second trenches into contact with an upper surface of the semiconductor layer.
    • 提供一种形成沟槽的方法,其包括提供具有半导体层或电介质层的叠层,金属氮化物层,流平层和第一掩模层。 通过第一掩模层和流平层蚀刻第一沟槽。 第一个掩模层被去除。 在平整层上形成第二掩模层。 通过第二掩模层形成第二沟槽,其中第二沟槽的基极不延伸穿过金属氮化物层。 去除第二掩模层。 金属氮化物层的暴露部分被选择性地蚀刻到半导体层和平整层的剩余部分,以使第一沟槽和第二沟槽延伸与半导体层的上表面接触。
    • 10. 发明申请
    • DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS
    • 双重接触跟踪只能分离分离过程
    • US20110049680A1
    • 2011-03-03
    • US12551801
    • 2009-09-01
    • Sean D. BurnsMatthew E. ColburnSteven J. Holmes
    • Sean D. BurnsMatthew E. ColburnSteven J. Holmes
    • H01L29/06G03F7/20H01L21/461
    • H01L21/31144G03F7/0035H01L21/0271H01L21/0338
    • An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.
    • 集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构,例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。 对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用 酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。 通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。