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21. 发明申请

US20140195743A1 ON-CHIP TRAFFIC PRIORITIZATION IN MEMORY 有权
标题翻译：内存中的片上交通优先
公开(公告)号：US20140195743A1
公开(公告)日：2014-07-10
申请号：US13737339
申请日：2013-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F13/18
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0625 , G06F3/0673 , G06F9/4881 , G06F13/1626 , G06F13/1663 , G06F13/18 , Y02D10/14
摘要： According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.
摘要翻译：根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控制器。存储器访问请求在存储器控制器处被接收。将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

22. 发明申请

US20140149673A1 LOW LATENCY DATA EXCHANGE 有权
公开(公告)号：US20140149673A1
公开(公告)日：2014-05-29
申请号：US13787057
申请日：2013-03-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , Y02D10/13
摘要： According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

23. 发明申请

US20140136895A1 EXPOSED-PIPELINE PROCESSING ELEMENT WITH ROLLBACK 有权
标题翻译：带滚筒的泄漏管道加工元件
公开(公告)号：US20140136895A1
公开(公告)日：2014-05-15
申请号：US13677746
申请日：2012-11-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F11/14
CPC分类号： G06F11/14 , G06F9/30036 , G06F9/30065 , G06F9/30116 , G06F9/3013 , G06F9/3863 , G06F9/3877 , G06F9/3887 , G06F11/1405 , G06F12/10 , Y02D10/13
摘要： An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.
摘要翻译：一个方面包括在暴露流水线处理元件中提供回滚支持。系统包括具有回滚支持逻辑的暴露流水线处理元件。回滚支持逻辑被配置为检测与暴露流水线处理元件中的指令的执行相关联的错误。回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

24. 发明授权

US10114652B2 Processor with hybrid pipeline capable of operating in out-of-order and in-order modes 有权
公开(公告)号：US10114652B2
公开(公告)日：2018-10-30
申请号：US15096805
申请日：2016-04-12
申请人： International Business Machines Corporation
发明人： Miguel Comparan , Andrew D. Hilton , Hans M. Jacobson , Brian M. Rogers , Robert A. Shearer , Ken V. Vu , Alfred T. Watson, III
IPC分类号： G06F9/38 , G06F9/30
摘要： A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

25. 发明授权

US09928190B2 High bandwidth low latency data exchange between processing elements 有权
公开(公告)号：US09928190B2
公开(公告)日：2018-03-27
申请号：US14739014
申请日：2015-06-15
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40 , G06F13/28 , G06F13/42 , G06F15/173
CPC分类号： G06F13/362 , G06F13/287 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G06F15/17337
摘要： Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

26. 发明授权

US09910802B2 High bandwidth low latency data exchange between processing elements 有权
公开(公告)号：US09910802B2
公开(公告)日：2018-03-06
申请号：US14948656
申请日：2015-11-23
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F13/00 , G06F13/362 , G06F13/40 , G06F13/28 , G06F13/42 , G06F15/173
CPC分类号： G06F13/362 , G06F13/287 , G06F13/4022 , G06F13/4068 , G06F13/4282 , G06F15/17337
摘要： Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing element chaining bus. The data is destined for another processing element via a data exchange component that is coupled between the first processing element and a second processing element via a communication line disposed between corresponding multiplexors of the first processing element and the second processing element. A further aspect includes determining, by the data exchange component, whether the data has been received at the data exchange element. If so, an indicator is set in a register of the data exchange component and the data is forwarded to the other processing element. Setting the indicator causes the first processing element to stall. If the data has not been received, the other processing element is stalled while the data exchange component awaits receipt of the data.

27. 发明申请

US20160239077A1 DELAYING EXECUTION IN A PROCESSOR TO INCREASE POWER SAVINGS 有权
公开(公告)号：US20160239077A1
公开(公告)日：2016-08-18
申请号：US15137184
申请日：2016-04-25
申请人： International Business Machines Corporation
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Augusto J. Vega
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： Embodiments relate to storing data in memory. An aspect includes applying a power savings technique to at least a subset of a processor. Pending work items scheduled to be executed by the processor are monitored. The pending work items are grouped based on the power savings technique. The grouping includes delaying a scheduled execution time of at least one of the pending work items to increase an overall number of clock cycles that the power savings technique is applied to the processor. It is determined that an execution criteria has been met. The pending work items are executed based on the execution criteria being met and the grouping.

28. 发明申请

US20160224351A1 PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES 审中-公开
标题翻译：具有混合管道的处理器可以在不合规格和订购模式下运行
公开(公告)号：US20160224351A1
公开(公告)日：2016-08-04
申请号：US15096805
申请日：2016-04-12
申请人： International Business Machines Corporation
发明人： Miguel Comparan , Andrew D. Hilton , Hans M. Jacobson , Brian M. Rogers , Robert A. Shearer , Ken V. Vu , Alfred T. Watson
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3867 , G06F9/30079 , G06F9/30145 , G06F9/30189 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3869 , G06F9/3873
摘要： A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.
摘要翻译：方法和电路装置为在无序和有序模式之间动态切换的混合流水线提供支持。混合流水线可以选择性地执行来自至少一个指令流的指令，该指令流需要在无序模式中通过无序处理提供的高性能能力。混合流水线还可以执行在按顺序模式中具有严格功率需求的指令，其中按顺序模式节省与无序模式相比的更多功率。当混合管道处于无序模式时，混合流水线中的每个级可以被激活并且完全功能。然而，当混合流水线从无序模式动态地切换到按顺序模式时，混合流水线中不用于按顺序模式的阶段可被停用并被指令旁路。然后当混合流水线从按顺序模式动态地切换到无序模式时，可以重新激活停用级。

29. 发明授权

US09405712B2 On-chip traffic prioritization in memory 有权
标题翻译：内存中的片上流量优先级
公开(公告)号：US09405712B2
公开(公告)日：2016-08-02
申请号：US13761252
申请日：2013-02-07
申请人： International Business Machines Corporation
发明人： Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F12/00 , G06F13/18 , G06F9/48 , G06F13/16
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0625 , G06F3/0673 , G06F9/4881 , G06F13/1626 , G06F13/1663 , G06F13/18 , Y02D10/14
摘要： According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.
摘要翻译：根据一个实施例，提供了一种存储器件。存储器件包括耦合到交叉开关互连的处理元件。处理元件被配置为向交叉开关互连发送包括优先级值的存储器访问请求。交叉开关互连被配置为将存储器访问请求路由到与存储器访问请求相关联的存储器控制器。存储器控制器耦合到存储器和交叉开关互连。存储器控制器包括队列，并被配置为将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求并执行下一个存储器基于最高优先级存储器访问请求的访问请求。

30. 发明授权

US09329664B2 Power management for a computer system 有权
公开(公告)号：US09329664B2
公开(公告)日：2016-05-03
申请号：US13966414
申请日：2013-08-14
申请人： International Business Machines Corporation
发明人： Pradip Bose , Bruce M. Fleischer , Thomas W. Fox , Hans M. Jacobson , Ravi Nair
IPC分类号： G06F1/00 , G06F1/32 , G06F9/48 , G06F9/44 , G06F9/38 , G06F13/16 , G06F3/06 , G06F13/00
CPC分类号： G06F1/3243 , G06F1/3228 , G06F1/3234 , G06F1/3275 , G06F1/3278 , G06F3/0656 , G06F9/3877 , G06F9/44 , G06F9/4893 , G06F13/00 , G06F13/1663 , G06F2212/312 , Y02D10/152 , Y02D10/24 , Y02D50/20
摘要： Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor executing a program on a program thread, encountering a first section of code to be executed by the active memory device, changing, by a first command, a power state of a powered unit on the active memory device based on the main processor encountering the first section of code, the first command including a store command. The method also includes the processing element executing the first section of code at a second time, changing a power state of the main processor from a power use state to a power saving state based on the processing element executing the first section.

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