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1. 发明授权

US10680892B2 Managing servers with quality of service assurances 有权
公开(公告)号：US10680892B2
公开(公告)日：2020-06-09
申请号：US16397302
申请日：2019-04-29
申请人： International Business Machines Corporation
发明人： Ganesh Balakrishnan , Mohammad Peyravian , Srinivasan Ramani , Brian M. Rogers , Ken V. Vu
IPC分类号： H04L12/24 , H04L12/927 , H04L29/08
摘要： Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

2. 发明授权

US09541985B2 Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints 有权
标题翻译：服务质量（QoS）/性能约束下的多核处理器中的节能优化
公开(公告)号：US09541985B2
公开(公告)日：2017-01-10
申请号：US14104154
申请日：2013-12-12
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Heather L. Hanson , David J. Palframan , Srinivasan Ramani , Ken V. Vu
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
摘要翻译：提供了一种用于优化一组处理器核心中的能量效率的机制，同时保持一组应用的应用性能。在该组应用程序中接收到一个或多个活动应用程序的服务质量（QoS）级别，并且识别与该组处理器核心中的每个处理器核心相关联的状态信息。响应于QoS级别和指示要实现的动作的状态信息，实施改变以减少数据处理系统中的一组处理器核心中的一个或多个处理器核心的功率利用率，其中该变化是经由至少一个的动态频率缩放，动态电压缩放或核心折叠。

3. 发明授权

US09378069B2 Lock spin wait operation for multi-threaded applications in a multi-core computing environment 有权
标题翻译：在多核心计算环境中为多线程应用程序锁定旋转等待操作
公开(公告)号：US09378069B2
公开(公告)日：2016-06-28
申请号：US14197581
申请日：2014-03-05
申请人： International Business Machines Corporation
发明人： Men-Chow Chiang , Ken V. Vu
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/526 , G06F9/4856
摘要： A method, system and computer-usable medium are disclosed for a lock-spin-wait operation for managing multi-threaded applications in a multi-core computing environment. A target processor core, referred to as a “spin-wait core” (SWC), is assigned (or reserved) for primarily running spin-waiting threads. Threads operating in the multi-core computing environment that are identified as spin-waiting are then moved to a run queue associated with the SWC to acquire a lock. The spin-waiting threads are then allocated a lock response time that is less than the default lock response time of the operating system (OS) associated with the SWC. If a spin-waiting fails to acquire a lock within the allocated lock response time, the SWC is relinquished, ceding its availability for other spin-waiting threads in the run queue to acquire a lock. Once a spin-waiting thread acquires a lock, it is migrated to its original, or an available, processor core.
摘要翻译：公开了用于在多核计算环境中管理多线程应用程序的锁 - 旋转等待操作的方法，系统和计算机可用介质。被称为“自旋等待核心”（SWC）的目标处理器核心被分配（或保留）用于主要运行的旋转等待线程。在多核心计算环境中运行的被识别为自转等待的线程随后被移动到与SWC相关联的运行队列以获取锁定。然后，旋转等待线程被分配的锁响应时间小于与SWC相关联的操作系统（OS）的默认锁响应时间。如果自动等待无法在分配的锁定响应时间内获取锁定，则SWC将被放弃，将其在运行队列中的其他旋转等待线程的可用性取消锁定。一旦旋转等待线程获取锁定，它将迁移到其原始处理器核心或可用的处理器核心。

4. 发明申请

US20190034208A1 PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES 审中-公开
公开(公告)号：US20190034208A1
公开(公告)日：2019-01-31
申请号：US16150051
申请日：2018-10-02
申请人： International Business Machines Corporation
发明人： Miguel Comparan , Andrew D. Hilton , Hans M. Jacobson , Brian M. Rogers , Robert A. Shearer , Ken V. Vu , Alfred T. Watson, III
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3867 , G06F9/30079 , G06F9/30145 , G06F9/30189 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/3869 , G06F9/3873
摘要： A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

5. 发明申请

US20160098299A1 GLOBAL LOCK CONTENTION PREDICTOR 有权
标题翻译：全球锁定预测器
公开(公告)号：US20160098299A1
公开(公告)日：2016-04-07
申请号：US14735481
申请日：2015-06-10
申请人： International Business Machines Corporation
发明人： Ganesh Balakrishnan , Srinivasan Ramani , Brian M. Rogers , Ken V. Vu
IPC分类号： G06F9/50
CPC分类号： G06F9/52 , G06F9/466 , G06F9/5016 , G06F9/526 , G06F9/528
摘要： A method for lock acquisition includes adding a current contention state of a lock to a contention history. The lock includes a memory location for storing information used for excluding accessing a resource by one or more threads while another thread accesses the resource. The method includes combining the contention history with a lock address for the lock to form a predictor table index, and using the predictor table index to determine a lock prediction for the lock. The prediction includes a determination of an amount of contention.
摘要翻译：一种用于锁获取的方法包括将锁的当前争用状态添加到争用历史。该锁包括用于存储用于在另一个线程访问该资源时排除一个或多个线程访问资源的信息的存储位置。该方法包括将争用历史与锁定的锁定地址组合以形成预测器表索引，并且使用预测器表索引来确定锁的锁定预测。该预测包括确定竞争量。

6. 发明申请

US20150169035A1 Energy Efficient Optimization in Multicore Processors Under Quality of Service (QoS)/Performance Constraints 有权
标题翻译：服务质量（QoS）/性能约束下的多核处理器中的能效优化
公开(公告)号：US20150169035A1
公开(公告)日：2015-06-18
申请号：US14304411
申请日：2014-06-13
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Heather L. Hanson , David J. Palframan , Srinivasan Ramani , Ken V. Vu
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
摘要翻译：提供了一种用于优化一组处理器核心中的能量效率的机制，同时保持一组应用的应用性能。在该组应用程序中接收到一个或多个活动应用程序的服务质量（QoS）级别，并且识别与该组处理器核心中的每个处理器核心相关联的状态信息。响应于QoS级别和指示要实现的动作的状态信息，实施改变以减少数据处理系统中的一组处理器核心中的一个或多个处理器核心的功率利用率，其中该变化经由至少一个的动态频率缩放，动态电压缩放或核心折叠。

7. 发明申请

US20150169032A1 Energy Efficient Optimization in Multicore Processors Under Quality of Service (QoS)/Performance Constraints 有权
标题翻译：服务质量（QoS）/性能约束下的多核处理器中的能效优化
公开(公告)号：US20150169032A1
公开(公告)日：2015-06-18
申请号：US14104154
申请日：2013-12-12
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Heather L. Hanson , David J. Palframan , Srinivasan Ramani , Ken V. Vu
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of sendee (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and die state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
摘要翻译：提供了一种用于优化一组处理器核心中的能量效率的机制，同时保持一组应用的应用性能。识别该组应用程序中的一个或多个活动应用程序的收件人（QoS）级别的质量，并识别与处理器核心集合中的每个处理器核心相关联的状态信息。响应于指示要实现的动作的QoS级别和管芯状态信息，实现改变以减少数据处理系统中的一组处理器核心中的一个或多个处理器核心的功率利用率，其中，所述处理器核心经由至少一个的动态频率缩放，动态电压缩放或核心折叠。

8. 发明授权

US09948513B2 Managing servers with quality of service assurances 有权
公开(公告)号：US09948513B2
公开(公告)日：2018-04-17
申请号：US14656816
申请日：2015-03-13
申请人： International Business Machines Corporation
发明人： Ganesh Balakrishnan , Mohammad Peyravian , Srinivasan Ramani , Brian M. Rogers , Ken V. Vu
IPC分类号： H04L12/24 , H04L12/927 , H04L29/08
CPC分类号： H04L41/0833 , H04L41/0893 , H04L47/805 , H04L67/1008 , H04L67/1023 , H04L67/322
摘要： Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

9. 发明授权

US09535486B2 Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints 有权
公开(公告)号：US09535486B2
公开(公告)日：2017-01-03
申请号：US14304411
申请日：2014-06-13
申请人： International Business Machines Corporation
发明人： Malcolm S. Allen-Ware , Heather L. Hanson , David J. Palframan , Srinivasan Ramani , Ken V. Vu
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.

10. 发明授权

US09323574B2 Processor power optimization with response time assurance 有权
标题翻译：处理器电源优化，响应时间保证
公开(公告)号：US09323574B2
公开(公告)日：2016-04-26
申请号：US14185974
申请日：2014-02-21
申请人： International Business Machines Corporation
发明人： Ganesh Balakrishnan , Mohammad Peyravian , Srinivasan Ramani , Brian M. Rogers , Ken V. Vu
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48
CPC分类号： G06F9/4893 , G06F1/329 , G06F9/5011 , G06F9/5027 , G06F9/5094 , Y02D10/22
摘要： A method for managing processor power optimization is provided. The method may include receiving a plurality of tasks for processing by a processor environment. The method may also include allocating a portion of a compute resource corresponding to the processor environment to each of the received plurality of tasks, the allocating of the portion being based on both an execution time and a response time associated with each of the received plurality of tasks.
摘要翻译：提供了一种管理处理器功率优化的方法。该方法可以包括接收由处理器环境处理的多个任务。该方法还可以包括将与处理器环境相对应的计算资源的一部分分配给接收到的多个任务中的每一个，该部分的分配基于与所接收的多个任务中的每一个相关联的执行时间和响应时间任务。

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