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21. 发明授权

US07898266B2 Probe with electrostatic actuation and capacitive sensor 有权
标题翻译：探头带有静电驱动和电容传感器
公开(公告)号：US07898266B2
公开(公告)日：2011-03-01
申请号：US12132665
申请日：2008-06-04
申请人： Wayne Allen Bonin , Dadi Setiadi , Lance Eugene Stover
发明人： Wayne Allen Bonin , Dadi Setiadi , Lance Eugene Stover
IPC分类号： G01R27/26 , G01B5/28
CPC分类号： G01R1/06794
摘要： A supported probe device that has a probe tip and probe body, the probe body having a sample facing surface and an opposing surface. The probe tip and a first electrode are on the sample facing surface. A second electrode is present on the probe body opposing surface. A third electrode is spaced from the second electrode, so that the second electrode is between the third electrode and the probe body. A first DC voltage source is electrically coupled to the first electrode, as is a first sensing circuit. A second DC voltage source is electrically coupled to the second electrode, and an AC voltage source electrically coupled to the third electrode. The probe body may be cantilevered.
摘要翻译：支撑的探针装置，其具有探针尖端和探针主体，探针主体具有面向样品的表面和相对的表面。探针尖端和第一电极位于面向样品的表面上。第二电极存在于探针体相对表面上。第三电极与第二电极间隔开，使得第二电极位于第三电极和探针体之间。第一直流电压源电耦合到第一电极，如第一感测电路一样。第二DC电压源电耦合到第二电极，以及电耦合到第三电极的AC电压源。探针体可以是悬臂的。

22. 发明申请

US20110007588A1 Defective Bit Scheme for Multi-Layer Integrated Memory Device 有权
标题翻译：多层集成存储器件缺陷位方案
公开(公告)号：US20110007588A1
公开(公告)日：2011-01-13
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00 , G11C29/04 , G11C15/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

23. 发明申请

US20100109153A1 HIGH BANDWIDTH PACKAGE 有权
标题翻译：高带包
公开(公告)号：US20100109153A1
公开(公告)日：2010-05-06
申请号：US12264522
申请日：2008-11-04
申请人： Dadi Setiadi , Patrick Ryan
发明人： Dadi Setiadi , Patrick Ryan
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L23/3128 , H01L24/48 , H01L25/0657 , H01L25/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/0652 , H01L2225/06572 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.
摘要翻译：在诸如数据存储设备的电子设备中构造和操作高带宽封装的方法和装置。在一些实施例中，高带宽封装包括具有通道功能的第一已知的良好裸片，具有控制器功能的第二已知的裸片以及具有缓冲功能的第三已知的裸片。此外，在一些实施例中，高带宽封装具有连接到第一，第二和第三裸片中的每一个的引脚。

24. 发明授权

US08617952B2 Vertical transistor with hardening implatation 有权
标题翻译：垂直晶体管与硬化插入
公开(公告)号：US08617952B2
公开(公告)日：2013-12-31
申请号：US12891966
申请日：2010-09-28
申请人： Young Pil Kim , Hyung-Kew Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
发明人： Young Pil Kim , Hyung-Kew Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
IPC分类号： H01L21/336
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/1206
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱状晶体管。然后将硬化物质注入垂直柱晶体管顶表面。然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

25. 发明授权

US08460794B2 Self-aligned wafer bonding 有权
标题翻译：自对准晶片接合
公开(公告)号：US08460794B2
公开(公告)日：2013-06-11
申请号：US12500892
申请日：2009-07-10
申请人： Jun Zheng , Dadi Setiadi
发明人： Jun Zheng , Dadi Setiadi
IPC分类号： B32B9/00 , B32B33/00
CPC分类号： B32B7/005 , B23K31/02 , H01L21/187 , H01L23/29 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05571 , H01L2224/13022 , H01L2224/131 , H01L2224/13147 , H01L2224/16111 , H01L2224/16147 , H01L2224/81002 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81805 , H01L2224/94 , H01L2225/06513 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01322 , Y10T428/24562 , Y10T428/24802 , Y10T428/24851 , Y10T428/24917 , Y10T428/31504 , Y10T428/31678 , H01L2224/81001 , H01L2224/05552
摘要： A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.
摘要翻译：晶片制品包括衬底，设置在衬底上的两个或更多个亲水区域，围绕亲水区域的疏水区域以及设置在衬底上的共晶接合材料。公开了包括具有互补的亲水区域和共晶接合材料的两个晶片的晶片装置，并且公开了形成接合晶片制品的方法。

26. 发明授权

US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08183126B2
公开(公告)日：2012-05-22
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L21/30
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

27. 发明申请

US20120074488A1 VERTICAL TRANSISTOR WITH HARDENING IMPLATATION 有权
标题翻译：具硬化强度的垂直晶体管
公开(公告)号：US20120074488A1
公开(公告)日：2012-03-29
申请号：US12891966
申请日：2010-09-28
申请人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
发明人： Young Pil Kim , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , Maroun Georges Khoury , Dadi Setiadi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L45/1233 , H01L27/228 , H01L27/2454 , H01L45/1206
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。然后将硬化物质注入垂直柱晶体管顶表面。然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。

28. 发明申请

US20100140790A1 CHIP HAVING THERMAL VIAS AND SPREADERS OF CVD DIAMOND 审中-公开
标题翻译：具有CVD金刚石的热水和散热片的芯片
公开(公告)号：US20100140790A1
公开(公告)日：2010-06-10
申请号：US12500268
申请日：2009-07-09
申请人： Dadi Setiadi , Hongyue Liu
发明人： Dadi Setiadi , Hongyue Liu
IPC分类号： H01L23/373 , H01L23/48 , H01L23/52
CPC分类号： H05K1/0206 , H01L23/3677 , H01L23/3732 , H01L23/49551 , H01L24/48 , H01L25/0657 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/06589 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/1305 , H01L2924/14 , H01L2924/181 , H05K3/42 , H05K2201/10689 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.
摘要翻译：一种具有散热器的集成电路芯片，其包括沿着芯片支撑体延伸的CVD金刚石和在没有有源器件或功能元件的区域中延伸穿过支撑体的热通孔。热通孔可以是导热的和导电的，或者可以是导热的和电阻的。集成电路芯片可以是3D集成电路芯片。

29. 发明授权

US08435827B2 Programmable resistive memory cell with sacrificial metal 有权
标题翻译：具有牺牲金属的可编程电阻存储单元
公开(公告)号：US08435827B2
公开(公告)日：2013-05-07
申请号：US13348255
申请日：2012-01-11
申请人： Venkatram Venkatasamy , Ming Sun , Dadi Setiadi
发明人： Venkatram Venkatasamy , Ming Sun , Dadi Setiadi
IPC分类号： H01L21/00
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/16 , H01L45/1608
摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.
摘要翻译：可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。牺牲金属设置在电化学活性电极和惰性电极之间。牺牲金属具有比成丝金属更负的标准电极电位。

30. 发明申请

US20120243311A1 Non-Sequential Encoding Scheme for Multi-Level Cell (MLC) Memory Cells 有权
标题翻译：用于多级单元（MLC）存储单元的非顺序编码方案
公开(公告)号：US20120243311A1
公开(公告)日：2012-09-27
申请号：US13070021
申请日：2011-03-23
申请人： Yiran Chen , Dadi Setiadi , Patrick J. Ryan
发明人： Yiran Chen , Dadi Setiadi , Patrick J. Ryan
IPC分类号： G11C16/04 , G11C11/14
CPC分类号： G11C11/161 , G11C7/1006 , G11C11/5607 , G11C11/5628 , G11C16/0483 , G11C2211/5648
摘要： Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.
摘要翻译：用于管理多层单元（MLC）存储单元阵列的装置和方法。根据各种实施例，选择非顺序编码方案，其相对于与所述多个存储器单元中的每一个相关联的写入功率，将所选择的MLC存储器单元的多个可用物理状态中的每一个分配给不同的多位逻辑值物理状态相关于所选择的非顺序编码方案，数据被写入所选择的MLC存储器单元。在一些实施例中，MLC存储器单元包括自旋转矩传递随机存取存储器（STRAM）存储器单元。在其他实施例中，MLC存储器单元包括MLC闪存单元。

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