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1. 发明授权

US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08183126B2
公开(公告)日：2012-05-22
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L21/30
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

2. 发明申请

US20120199915A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 审中-公开
标题翻译：用于垂直堆叠半导体元件的嵌入式控制线图案化
公开(公告)号：US20120199915A1
公开(公告)日：2012-08-09
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L27/105
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

3. 发明授权

US08896070B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08896070B2
公开(公告)日：2014-11-25
申请号：US13446462
申请日：2012-04-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L45/00 , H01L27/24 , H01L27/22 , H01L43/08 , H01L27/10
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

4. 发明申请

US20110006377A1 Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements 有权
标题翻译：用于垂直堆叠半导体元件的嵌入式控制线图案化
公开(公告)号：US20110006377A1
公开(公告)日：2011-01-13
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L27/105 , H01L21/18
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

5. 发明申请

US20120080725A1 VERTICAL TRANSISTOR MEMORY ARRAY 审中-公开
标题翻译：垂直晶体管存储阵列
公开(公告)号：US20120080725A1
公开(公告)日：2012-04-05
申请号：US12894405
申请日：2010-09-30
申请人： Peter Nicholas Manos , Young Pil Kim , Hyung-Kyu Lee , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir , Brian Lee , Dadi Setiadi
发明人： Peter Nicholas Manos , Young Pil Kim , Hyung-Kyu Lee , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir , Brian Lee , Dadi Setiadi
IPC分类号： H01L27/08 , H01L21/02
CPC分类号： H01L27/101 , G11C11/16 , H01L21/823487 , H01L27/228 , H01L27/2454 , H01L2924/0002 , H01L2924/00
摘要： A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.
摘要翻译：一种方法包括提供具有从半导体晶片正交延伸的多个柱结构的半导体晶片。导电互连元件沉积在至少选定的垂直柱晶体管上，并且非挥发性可变电阻存储单元沉积在导电互连层上以形成垂直晶体管存储器阵列。

6. 发明申请

US20100109085A1 MEMORY DEVICE DESIGN 审中-公开
标题翻译：内存设备设计
公开(公告)号：US20100109085A1
公开(公告)日：2010-05-06
申请号：US12408112
申请日：2009-03-20
申请人： Jinyoung Kim , Yongchul Ahn , Muralikrishnan Balakrishnan , Tangshiun Yeh , Antoine Khoueir
发明人： Jinyoung Kim , Yongchul Ahn , Muralikrishnan Balakrishnan , Tangshiun Yeh , Antoine Khoueir
IPC分类号： H01L29/40 , H01L21/4763
CPC分类号： H01L45/085 , H01L43/08 , H01L43/12 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： Memory elements and methods for making memory elements. One method of making a memory element includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell. The memory elements may be resistance random access memory elements.
摘要翻译：记忆元素和制作记忆元素的方法。制造存储元件的一种方法包括形成第一电极，在第一电极，存储单元和彼此相邻的电流致密元件上形成导电电流致密元件和存储单元。在电流致密元件和存储单元上形成第二电极。存储器元件可以是电阻随机存取存储器元件。

7. 发明申请

US20110007538A1 SYSTEMS AND METHODS OF CELL SELECTION IN CROSS-POINT ARRAY MEMORY DEVICES 有权
标题翻译：跨点阵列存储器件中的细胞选择的系统和方法
公开(公告)号：US20110007538A1
公开(公告)日：2011-01-13
申请号：US12502111
申请日：2009-07-13
申请人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
发明人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C13/0023 , G11C5/02 , G11C13/0038 , G11C2213/71
摘要： The disclosure is related to three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).
摘要翻译：本公开涉及三维交叉点阵列存储器件并选择三维交叉点阵列存储器内的单元。在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。

8. 发明授权

US08514637B2 Systems and methods of cell selection in three-dimensional cross-point array memory devices 有权
标题翻译：三维交叉点阵列存储器件中细胞选择的系统和方法
公开(公告)号：US08514637B2
公开(公告)日：2013-08-20
申请号：US12502111
申请日：2009-07-13
申请人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
发明人： Chulmin Jung , Jinyoung Kim , Yong Lu , Harry Liu
IPC分类号： G11C7/00
CPC分类号： G11C13/0023 , G11C5/02 , G11C13/0038 , G11C2213/71
摘要： Three dimensional cross-point array memory devices and selecting cells within a three dimensional cross-point array memory. In a particular embodiment, three different voltages levels are applied to bit lines of the cross point array to allow for selection of a specific cell. Series of select devices may be implemented to provide a high voltage and a low voltage to specific bit lines, while a middle voltage may also be provided. In a particular embodiment, the select devices comprise Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).
摘要翻译：三维交叉点阵列存储器件，并选择三维交叉点阵列存储器内的单元。在特定实施例中，将三个不同的电压电平施加到交叉点阵列的位线以允许选择特定单元。可以实现一系列选择装置以向特定位线提供高电压和低电压，同时还可以提供中间电压。在特定实施例中，选择器件包括金属氧化物半导体场效应晶体管（MOSFET）。

9. 发明申请

US20110007039A1 PLASMA DISPLAY APPARATUS 审中-公开
标题翻译：等离子显示设备
公开(公告)号：US20110007039A1
公开(公告)日：2011-01-13
申请号：US12673739
申请日：2008-04-25
申请人： Heekwon Kim , Jinyoung Kim
发明人： Heekwon Kim , Jinyoung Kim
IPC分类号： G09G5/00
CPC分类号： G09G3/293 , G09G2310/0216 , G09G2310/0218 , G09G2310/0267 , G09G2310/0283 , G09G2320/0228
摘要： A plasma display apparatus is disclosed. The plasma display apparatus includes a plasma display panel and a driver. The plasma display panel includes a front substrate on which a plurality of scan electrodes and a plurality of sustain electrode are positioned substantially parallel to each other, a rear substrate on which a plurality of address electrodes are positioned to intersect the scan electrodes and the sustain electrodes, and a phosphor layer that is positioned between the front substrate and the rear substrate and includes a phosphor material and MgO material. The driver supplies scan signals to the plurality of scan electrodes at different times of an address period of a subfield in an active area.
摘要翻译：公开了一种等离子体显示装置。等离子体显示装置包括等离子体显示面板和驱动器。等离子体显示面板包括前面基板，多个扫描电极和多个维持电极基本上彼此平行地定位在其上，多个寻址电极定位在其上的后基板与扫描电极和维持电极相交以及位于前基板和后基板之间的荧光体层，并且包括荧光体材料和MgO材料。驱动器在有源区域中的子场的寻址周期的不同时间向多个扫描电极提供扫描信号。

10. 发明授权

US07633467B2 Plasma display apparatus and driving method thereof 失效
标题翻译：等离子体显示装置及其驱动方法
公开(公告)号：US07633467B2
公开(公告)日：2009-12-15
申请号：US11283906
申请日：2005-11-22
申请人： Janghwan Cho , Donghyuk Park , Changyoung Kwon , Dong Kwon Choi , Yang Ki An , Jinyoung Kim , Yunkwon Jung
发明人： Janghwan Cho , Donghyuk Park , Changyoung Kwon , Dong Kwon Choi , Yang Ki An , Jinyoung Kim , Yunkwon Jung
IPC分类号： G09G3/28
CPC分类号： G09G3/2965 , G09G3/293
摘要： A plasma display apparatus and a driving method thereof are disclosed. The plasma display apparatus comprises a plasma display panel in which a plurality of electrodes are formed, an energy storage unit for storing energy applied to the electrodes, and a protector for maintaining a voltage level of the energy stored in the energy storage unit at a predetermined voltage range.
摘要翻译：公开了一种等离子体显示装置及其驱动方法。等离子体显示装置包括：等离子体显示面板，其中形成有多个电极;能量存储单元，用于存储施加到电极的能量;以及保护器，用于将存储在能量存储单元中的能量的电压水平保持在预定的电压范围

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