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21. 发明授权

US6096629A Uniform sidewall profile etch method for forming low contact leakage schottky diode contact 有权
公开(公告)号：US6096629A
公开(公告)日：2000-08-01
申请号：US187301
申请日：1998-11-05
申请人： Jun-Lin Tsai , Yen-Shih Ho
发明人： Jun-Lin Tsai , Yen-Shih Ho
IPC分类号： H01L21/285 , H01L21/311 , H01L21/768 , H01L21/28
CPC分类号： H01L21/28537 , H01L21/31116 , H01L21/76804
摘要： A method for forming a Schottky diode. There is first provided a silicon layer. There is then formed upon the silicon layer an anisotropically patterned first dielectric layer which defines a Schottky diode contact region of the silicon layer. There is then formed and aligned upon the anisotropically patterned first dielectric layer a patterned second dielectric layer which is formed of a thermally reflowable material. There is then reflowed thermally the patterned second dielectric layer to form a thermally reflowed patterned second dielectric layer having a uniform sidewall profile with respect to the anisotropically patterned first dielectric layer while simultaneously forming a thermal silicon oxide layer upon the Schottky diode contact region of the silicon layer. There is then etched while employing a first etch method the thermal silicon oxide layer from the Schottky diode contact region of the silicon layer while preserving the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer. There is then formed and thermally annealed upon the thermally reflowed patterned second dielectric layer and the Schottky diode contact region of the silicon layer a metal silicide forming metal layer to form in a self aligned fashion a metal silicide layer upon the Schottky diode contact region of the silicon layer, a protective oxide surface layer upon the metal silicide layer and a metal silicide forming metal layer residue upon the thermally reflowed patterned second dielectric layer. There is then stripped from the thermally reflowed patterned second dielectric layer the metal silicide forming metal layer residue. Finally, there is then etched while employing a second etch method the protective oxide surface layer from the metal silicide layer, where the second etch method also preserves the uniform sidewall profile of the thermally reflowed patterned second dielectric layer with respect to the anisotropically patterned first dielectric layer.

22. 发明授权

US09711403B2 Method for forming chip package 有权
公开(公告)号：US09711403B2
公开(公告)日：2017-07-18
申请号：US13352234
申请日：2012-01-17
申请人： Chien-Hui Chen , Ming-Kun Yang , Tsang-Yu Liu , Yen-Shih Ho
发明人： Chien-Hui Chen , Ming-Kun Yang , Tsang-Yu Liu , Yen-Shih Ho
IPC分类号： H01L21/78 , H01L21/768 , H01L23/48 , H01L23/31 , H01L23/00
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3121 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/73253 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/00014 , H01L2924/00
摘要： An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

23. 发明授权

US08779452B2 Chip package 有权
标题翻译：芯片封装
公开(公告)号：US08779452B2
公开(公告)日：2014-07-15
申请号：US13224267
申请日：2011-09-01
申请人： Tzu-Hsiang Hung , Hsin-Chih Chiu , Chuan-Jin Shiu , Chia-Sheng Lin , Yen-Shih Ho , Yu-Min Liang
发明人： Tzu-Hsiang Hung , Hsin-Chih Chiu , Chuan-Jin Shiu , Chia-Sheng Lin , Yen-Shih Ho , Yu-Min Liang
IPC分类号： H01L29/22
CPC分类号： H01L27/14618 , H01L2224/13 , H01L2224/13022 , H01L2224/131 , H01L2924/13091 , H01L2924/1461 , H01L2933/0066 , H01L2924/014 , H01L2924/00
摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device disposed at the first surface; a protection layer disposed on the second surface of the substrate, wherein the protection layer has an opening; a conducting bump disposed on the second surface of the substrate and filled in the opening; a conducting layer disposed between the protection layer and the substrate, wherein the conducting layer electrically connects the optoelectronic device to the conducting bump; and a light shielding layer disposed on the protection layer, wherein the light shielding layer does not contact with the conducting bump.
摘要翻译：本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 设置在第一表面处的光电子器件; 保护层，设置在所述基板的第二表面上，其中所述保护层具有开口; 设置在所述基板的第二表面上并填充在所述开口中的导电凸块; 设置在所述保护层和所述基板之间的导电层，其中所述导电层将所述光电子器件电连接到所述导电凸块; 以及设置在保护层上的遮光层，其中遮光层不与导电凸块接触。

24. 发明授权

US08674518B2 Chip package and method for forming the same 有权
公开(公告)号：US08674518B2
公开(公告)日：2014-03-18
申请号：US13340162
申请日：2011-12-29
申请人： Shu-Ming Chang , Tsang-Yu Liu , Yen-Shih Ho
发明人： Shu-Ming Chang , Tsang-Yu Liu , Yen-Shih Ho
IPC分类号： H01L23/498 , H01L21/00
CPC分类号： H01L25/50 , B81C1/00238 , B81C2203/0785 , B81C2203/0792 , H01L21/76898 , H01L21/8221 , H01L23/10 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L2224/02372 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05548 , H01L2224/05554 , H01L2224/05567 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/13022 , H01L2224/13024 , H01L2224/1403 , H01L2224/14181 , H01L2224/14517 , H01L2224/17517 , H01L2224/73103 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01029 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/00012 , H01L2224/81 , H01L2924/00 , H01L2224/05552
摘要： An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

25. 发明授权

US08624362B2 IC wafer having electromagnetic shielding effects and method for making the same 有权
标题翻译：具有电磁屏蔽效果的IC晶片及其制造方法
公开(公告)号：US08624362B2
公开(公告)日：2014-01-07
申请号：US13219468
申请日：2011-08-26
申请人： Yao-Hsiang Chen , Tsang-Yu Liu , Yen-Shih Ho , Shu-Ming Chang
发明人： Yao-Hsiang Chen , Tsang-Yu Liu , Yen-Shih Ho , Shu-Ming Chang
IPC分类号： H01L21/60 , H01L23/498
CPC分类号： H01L23/552 , H01L21/71 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0346 , H01L2224/0361 , H01L2224/0401 , H01L2224/05572 , H01L2224/06155 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13144 , H01L2924/00013 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.
摘要翻译： IC晶片和IC晶片的制造方法，IC晶片包括具有多个焊盘和设置在其上的绝缘层的集成电路层，多个贯穿相应于焊盘的绝缘层的通孔，分别用于封装层的注入和形成在绝缘层的顶表面上并与用于电磁结构的集成电路层的焊盘电隔离的电磁屏蔽层。因此，集成电路不需要任何进一步的屏蔽掩模，从而简化制造。此外，通孔的设计有助于进一步的包装过程。

26. 发明授权

US08614488B2 Chip package and method for forming the same 有权
标题翻译：芯片封装及其形成方法
公开(公告)号：US08614488B2
公开(公告)日：2013-12-24
申请号：US13314114
申请日：2011-12-07
申请人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
发明人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2224/02372 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05672 , H01L2224/11002 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.
摘要翻译：芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点栅极导电结构基本上共面。

27. 发明授权

US06667217B1 Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process 有权
标题翻译：使用亚0.18μmCMOS工艺制造镶嵌铜电感器结构的方法
公开(公告)号：US06667217B1
公开(公告)日：2003-12-23
申请号：US09795115
申请日：2001-03-01
申请人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
发明人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/042 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.
摘要翻译：已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构，以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

28. 发明授权

US6051475A Method for manufacturing a silicide to silicide capacitor 失效
标题翻译：硅化物电容器的制造方法
公开(公告)号：US6051475A
公开(公告)日：2000-04-18
申请号：US089558
申请日：1998-06-03
申请人： Yen-Shih Ho , Chun-Hon Chen
发明人： Yen-Shih Ho , Chun-Hon Chen
IPC分类号： H01L21/02 , H01L21/28
CPC分类号： H01L28/40 , H01L28/60
摘要： A process is described for the manufacture of a capacitor having low V.sub.cc. Said process is fully compatible with standard IC manufacturing and introduces minimum modification thereto. The process involves the formation of a capacitor having both upper and lower electrodes that comprise layers of a metal silicide. The lower electrode is formed as a byproduct of the SALICIDE process while the upper electrode is formed by first laying down a layer of polysilicon followed by a layer of a silicide-forming metal such as titanium, cobalt, or tungsten. Sufficient of the metal must be provided to ensure that all of the polysilicon gets transformed to silicide.
摘要翻译：描述了制造具有低Vcc的电容器的工艺。所述方法与标准IC制造完全兼容，并对其进行最小修改。该方法包括形成具有包括金属硅化物层的上电极和下电极的电容器。下电极形成为SALICIDE工艺的副产物，而上电极通过首先铺设多晶硅层，然后形成诸如钛，钴或钨的硅化物形成金属层而形成。必须提供足够的金属以确保所有的多晶硅转变为硅化物。

29. 发明授权

US6004829A Method of increasing end point detection capability of reactive ion etching by adding pad area 失效
标题翻译：通过添加焊盘面积增加反应离子蚀刻终点检测能力的方法
公开(公告)号：US6004829A
公开(公告)日：1999-12-21
申请号：US928229
申请日：1997-09-12
申请人： Tzong-Sheng Chang , Yen-Shih Ho , Ruey-Hsin Liou , Yuan-Cheng Yu
发明人： Tzong-Sheng Chang , Yen-Shih Ho , Ruey-Hsin Liou , Yuan-Cheng Yu
IPC分类号： H01L21/311 , H01L21/66 , H01L21/8247 , H01L23/544 , H01L21/8238
CPC分类号： H01L27/11526 , H01L21/31116 , H01L22/26 , H01L22/34 , H01L27/11539 , H01L2924/0002
摘要： A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode detection is used in the etching process in a way in which the area exposed during etching is increased to enhance the end point detection capacity, by adding a surplus pad area before pad formation. Specifically an EPROM device is formed with a first level of polysilicon above a gate oxide layer patterned into a floating gate electrode of an EPROM device. Then form an ONO layer above the floating gate electrode. Define array protection, grow a second gate oxide layer, deposit a second level of polysilicon, define peripheral gates from the second level of polysilicon, and define an EPROM transistor gate electrode from the second level of polysilicon.
摘要翻译：形成半导体器件的方法包括在制造半导体器件中形成多晶硅层和电介质层，并使用光刻和蚀刻工艺步骤将层图案化成器件。在蚀刻工艺中使用端点模式检测，其中通过在焊盘形成之前添加剩余焊盘区域，在蚀刻期间暴露的区域增加以增强端点检测能力的方式。具体地说，EPROM器件形成有图案化为EPROM器件的浮置栅电极的栅极氧化物层上方的第一级多晶硅。然后在浮栅电极上形成ONO层。定义阵列保护，生长第二栅极氧化层，沉积第二级多晶硅，从第二级多晶硅定义外围栅极，并从第二级多晶硅定义EPROM晶体管栅电极。

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