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21. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

22. 发明申请

US20090057765A1 FINFET STRUCTURE USING DIFFERING GATE DIELECTRIC MATERIALS AND GATE ELECTRODE MATERIALS 有权
标题翻译： FINFET结构使用不同的门电介质材料和门电极材料
公开(公告)号：US20090057765A1
公开(公告)日：2009-03-05
申请号：US11847573
申请日：2007-08-30
申请人： Huilong Zhu , Bruce B. Doris , Ying Zhang
发明人： Huilong Zhu , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L29/785
摘要： A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.
摘要翻译：半导体结构包括第一finFET和第二finFET。第一finFET和第二finFET可以包括n-finFET和p-finFET，以提供CMOS finFET结构。在半导体结构内，以下至少一个：（1）第一鳍状FET内的第一栅极电介质和第二鳍状FET内的第二栅极电介质包括不同的栅极电介质材料; 和/或（2）第一鳍状FET内的第一栅电极和第二鳍状FET内的第二栅电极包括不同的栅电极材料。

23. 发明授权

US06914303B2 Ultra thin channel MOSFET 有权
公开(公告)号：US06914303B2
公开(公告)日：2005-07-05
申请号：US10650229
申请日：2003-08-28
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

24. 发明申请

US20050189589A1 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 有权
标题翻译：混合SOI / BULK半导体晶体管
公开(公告)号：US20050189589A1
公开(公告)日：2005-09-01
申请号：US10708378
申请日：2004-02-27
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L27/01 , H01L29/06 , H01L29/10 , H01L29/786
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

25. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

26. 发明申请

US20060091450A1 Dual function FinFET, finmemory and method of manufacture 有权
公开(公告)号：US20060091450A1
公开(公告)日：2006-05-04
申请号：US10978951
申请日：2004-11-01
申请人： Huilong Zhu , Bruce Doris , Jochen Beintner
发明人： Huilong Zhu , Bruce Doris , Jochen Beintner
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L29/78684 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/4908 , H01L29/66795 , H01L29/785 , H01L29/7881
摘要： A non-volatile storage cell in a Fin Field Effect Transistor (FinFET) and a method of forming an Integrated Circuit (IC) chip including the non-volatile storage cell. Each FET includes a control gate along one side of a semiconductor (e.g., silicon) fin, a floating gate along an opposite of the fin and a program gate alongside the floating gate. Control gate device thresholds are adjusted by adjusting charge on the floating gate.

27. 发明授权

US08497168B2 Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers 失效
标题翻译：使用不同种类的应力层来增强NFET和PFET性能的结构和方法
公开(公告)号：US08497168B2
公开(公告)日：2013-07-30
申请号：US13071940
申请日：2011-03-25
申请人： Bruce B. Doris , Haining Yang , Huilong Zhu
发明人： Bruce B. Doris , Haining Yang , Huilong Zhu
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率，取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

28. 发明授权

US08008724B2 Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers 有权
标题翻译：使用不同种类的应力层来增强nFET和pFET性能的结构和方法
公开(公告)号：US08008724B2
公开(公告)日：2011-08-30
申请号：US10695748
申请日：2003-10-30
申请人： Bruce B. Doris , Haining Yang , Huilong Zhu
发明人： Bruce B. Doris , Haining Yang , Huilong Zhu
IPC分类号： H01L23/62
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率，取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

29. 发明授权

US07326997B2 Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film 有权
标题翻译：用强调膜增强nMOSFET和pMOSFET性能的方法和结构
公开(公告)号：US07326997B2
公开(公告)日：2008-02-05
申请号：US11561047
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L27/01
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

30. 发明授权

US07314789B2 Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification 有权
标题翻译：用于产生MOSFET通道迁移率修正的局部机械栅极应力的结构和方法
公开(公告)号：US07314789B2
公开(公告)日：2008-01-01
申请号：US11618751
申请日：2006-12-30
申请人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
发明人： Cyril Cabral, Jr. , Bruce B. Doris , Thomas S. Kanarsky , Xiao H. Liu , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/84 , H01L21/04
CPC分类号： H01L29/7845 , H01L21/3215 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/665
摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.
摘要翻译：提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

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