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1. 发明授权

US07326997B2 Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film 有权
标题翻译：用强调膜增强nMOSFET和pMOSFET性能的方法和结构
公开(公告)号：US07326997B2
公开(公告)日：2008-02-05
申请号：US11561047
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L27/01
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

2. 发明授权

US07183613B1 Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film 有权
标题翻译：用应力膜增强NMOSFET和PMOSFET性能的方法和结构
公开(公告)号：US07183613B1
公开(公告)日：2007-02-27
申请号：US11164224
申请日：2005-11-15
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L27/01
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极堆叠每个都由在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

3. 发明授权

US07476579B2 Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film 有权
标题翻译：用强调膜增强nMOSFET和pMOSFET性能的方法和结构
公开(公告)号：US07476579B2
公开(公告)日：2009-01-13
申请号：US11560925
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce B. Doris , Zhibin Ren
IPC分类号： H01L21/336
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

4. 发明申请

US20070122961A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM 有权
标题翻译：用于增强半导体场效应晶体管的NMOSFET和PMOSFET性能的方法和结构
公开(公告)号：US20070122961A1
公开(公告)日：2007-05-31
申请号：US11560925
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

5. 发明申请

US20070120197A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WTH A STRESSED FILM 有权
标题翻译：用于增强NMOSFET和PMOSFET性能的方法和结构WTH A受压膜
公开(公告)号：US20070120197A1
公开(公告)日：2007-05-31
申请号：US11561047
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

6. 发明授权

US07494861B2 Method for metal gated ultra short MOSFET devices 失效
标题翻译：金属门极超短MOSFET器件的方法
公开(公告)号：US07494861B2
公开(公告)日：2009-02-24
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

7. 发明申请

US20080124860A1 Metal Gated Ultra Short MOSFET Devices 失效
标题翻译：金属栅极超短MOSFET器件
公开(公告)号：US20080124860A1
公开(公告)日：2008-05-29
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

8. 发明授权

US07678638B2 Metal gated ultra short MOSFET devices 失效
标题翻译：金属门极超短MOSFET器件
公开(公告)号：US07678638B2
公开(公告)日：2010-03-16
申请号：US12198857
申请日：2008-08-26
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

9. 发明申请

US20080318374A1 Metal Gated Ultra Short MOSFET Devices 失效
公开(公告)号：US20080318374A1
公开(公告)日：2008-12-25
申请号：US12198857
申请日：2008-08-26
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

10. 发明授权

US07348629B2 Metal gated ultra short MOSFET devices 有权
标题翻译：金属门极超短MOSFET器件
公开(公告)号：US07348629B2
公开(公告)日：2008-03-25
申请号：US11407473
申请日：2006-04-20
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

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