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21. 发明公开

US20240285244A1 DEEP RESIDUAL INCEPTION ENCODER-DECODER NETWORK FOR AMYLOID PET HARMONIZATION 审中-公开
公开(公告)号：US20240285244A1
公开(公告)日：2024-08-29
申请号：US18659581
申请日：2024-05-09
申请人： Fei Gao , Yi Su , Jay Shah , Teresa Wu
发明人： Fei Gao , Yi Su , Jay Shah , Teresa Wu
IPC分类号： A61B6/03 , G06T5/20 , G06T15/00 , H04N19/117 , H04N19/176
CPC分类号： A61B6/037 , G06T5/20 , G06T15/00 , H04N19/117 , H04N19/176
摘要： Using deep learning, imaging harmonization among images produced with differing PET tracers is achieved. A method may include providing an original PET image of the brain using an original PET tracer, providing a target PET tracer, and converting, using a deep learning neural network, the original PET image into a target PET image simulating the image that would be obtained had the target PET tracer been used.

22. 发明授权

US08829603B2 Shielded gate trench MOSFET package 有权
标题翻译：屏蔽栅沟MOSFET封装
公开(公告)号：US08829603B2
公开(公告)日：2014-09-09
申请号：US13212940
申请日：2011-08-18
申请人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Daniel Calafut , Anup Bhalla
IPC分类号： H01L29/66 , H01L23/64 , H01L29/78 , H01L29/40 , H01L29/423 , H01L23/00
CPC分类号： H01L29/7813 , H01L23/647 , H01L24/06 , H01L24/48 , H01L24/49 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2224/0603 , H01L2224/4813 , H01L2224/48247 , H01L2224/4911 , H01L2224/49111 , H01L2924/00014 , H01L2924/10253 , H01L2924/12032 , H01L2924/13091 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielded gate trench field effect transistor can be formed on a substrate having an epitaxial layer on the substrate and a body layer on the epitaxial layer. A trench formed in the body layer and epitaxial layer is lined with a dielectric layer. A shield electrode is formed within a lower portion of the trench. The shield electrode is insulated by the dielectric layer. A gate electrode is formed in the trench above the shield electrode and insulated from the shield electrode by an additional dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the one or more source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element can be electrically connected between the shield electrode pad and the source lead in the package.
摘要翻译：可以在衬底上具有外延层的衬底上形成屏蔽栅沟槽场效应晶体管，并在外延层上形成体层。形成在体层和外延层中的沟槽衬有介电层。屏蔽电极形成在沟槽的下部内。屏蔽电极由电介质层绝缘。栅极电极形成在屏蔽电极上方的沟槽中，并通过附加的介电层与屏蔽电极绝缘。形成在体层内的一个或多个源极区域与沟槽的侧壁相邻。形成在主体层上方的源极焊盘与一个或多个源极区域电连接并与栅电极和屏蔽电极绝缘。源极焊盘提供与源极区域的外部接触。栅极焊盘提供与栅电极的外部接触。屏蔽电极焊盘提供与屏蔽电极的外部接触。电阻元件可以电连接在封装中的屏蔽电极焊盘和源极引线之间。

23. 发明授权

US08802509B2 Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection 有权
标题翻译：门极漏极（GD）钳位和ESD保护电路的配置用于电源器件击穿保护
公开(公告)号：US08802509B2
公开(公告)日：2014-08-12
申请号：US12932584
申请日：2011-02-28
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/822
CPC分类号： H01L29/7813 , H01L27/0255 , H01L27/0629 , H01L29/0615 , H01L29/0638 , H01L29/0646 , H01L29/0692 , H01L29/0696 , H01L29/66734 , H01L29/7803 , H01L29/7804 , H01L29/7808 , H01L29/7811 , H01L29/7815 , H01L29/8611 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend.
摘要翻译：一种半导体功率器件，其被支撑在半导体衬底上，该半导体衬底包括多个晶体管单元，每个晶体管单元具有源极和漏极，栅极用于控制在源极和漏极之间传输的电流。半导体还包括在栅极和漏极之间串联连接的栅极 - 漏极（GD）钳位端接器，还包括串联连接到硅二极管的多个背对背多晶硅二极管，包括半导体中的并行掺杂的列衬底，其中平行掺杂的柱具有预定的间隙。掺杂的柱还包括U形弯曲柱，其将平行掺杂的柱的端部连接在一起，深度掺杂的阱设置在U形弯曲部下方并吞噬U形弯曲部。

24. 发明授权

US08764448B2 Robotic device for use in image-guided robot assisted surgical training 有权
标题翻译：用于图像引导机器人辅助外科手术的机器人装置
公开(公告)号：US08764448B2
公开(公告)日：2014-07-01
申请号：US13820065
申请日：2011-09-01
申请人： Tao Yang , Liangjing Yang , Jiang Liu , Chee Kong Chui , Weimin Huang , Jing Zhang , Jiayin Zhou , Beng Hai Lee , Ngan Meng Tan , Wing Kee Damon Wong , Fengshou Yin , Kin Yong Chang , Yi Su
发明人： Tao Yang , Liangjing Yang , Jiang Liu , Chee Kong Chui , Weimin Huang , Jing Zhang , Jiayin Zhou , Beng Hai Lee , Ngan Meng Tan , Wing Kee Damon Wong , Fengshou Yin , Kin Yong Chang , Yi Su
IPC分类号： G09B23/28 , A61B17/00 , G06G7/58 , A61B19/00
CPC分类号： G09B23/28 , A61B34/30 , B25J3/04 , B25J7/00 , G09B23/285
摘要： A robotic device for use in image-guided robot assisted surgical training, the robotic device comprising a manual interface structure configured to simulate handling of a surgical tool; a translational mechanism for translational motion of the manual interface structure; a rotational mechanism for rotational motion of the manual interface structure; and a spherical mechanism configured to decouple the orientation of the manual interface structure into spatial coordinates, wherein a linkage between the rotational mechanism, the rotational mechanism and the spherical mechanism, and the manual interface structure are disposed on opposing sides of an intersection of a pitch axis and a yaw axis of the spherical mechanism.
摘要翻译：一种用于图像引导机器人辅助外科手术训练的机器人装置，所述机器人装置包括被配置为模拟外科手术工具的处理的手动界面结构; 手动界面结构的平移运动的平移机制; 用于手动接口结构的旋转运动的旋转机构; 以及球面机构，被配置为将手动界面结构的取向分离成空间坐标，其中旋转机构，旋转机构和球面机构之间的联动以及手动界面结构设置在俯仰的交叉点的相对侧上轴和球面机构的偏转轴。

25. 发明授权

US08304315B2 Integration of a sense FET into a discrete power MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US08304315B2
公开(公告)日：2012-11-06
申请号：US13149051
申请日：2011-05-31
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：主FET和一个或多个感测FET形成在公共衬底中。主FET和感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和检测FET的栅极端子。电隔离可以在主FET的栅极端子和感测FET之间。与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

26. 发明申请

US20090166740A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20090166740A1
公开(公告)日：2009-07-02
申请号：US12006398
申请日：2007-12-31
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

27. 发明申请

US20070106935A1 Apparatus and method for implementing flexible page layout 审中-公开
标题翻译：实现灵活页面布局的装置和方法
公开(公告)号：US20070106935A1
公开(公告)日：2007-05-10
申请号：US11580209
申请日：2006-10-12
申请人： Yi Su , Jianjun Liu , Yongsheng Guo , Zhixiong Zhang
发明人： Yi Su , Jianjun Liu , Yongsheng Guo , Zhixiong Zhang
IPC分类号： G06F17/00
CPC分类号： G06F17/248 , G06F16/9577 , G06F17/212
摘要： An apparatus and a method for implementing a flexible page layout. The apparatus includes: a page presentation unit, for providing at least one presentation mode of the page layout; a page control unit connected with the page presentation unit, for selecting resources supported by the user terminal, loading the resources to the page presentation unit, and generating a display page for providing to the user. The method includes: providing at least one presentation mode of the page layout; selecting resources supported by the user terminal, loading the resources according to the at least one presentation mode, and generating a display page. According to the invention, page layout diversification may be realized and various types of contents may be loaded in a page flexibly.
摘要翻译：一种用于实现灵活页面布局的设备和方法。该装置包括：页面呈现单元，用于提供页面布局的至少一个呈现模式; 与页面呈现单元连接的页面控制单元，用于选择用户终端支持的资源，将资源加载到页面呈现单元，以及生成用于提供给用户的显示页面。该方法包括：提供页面布局的至少一个呈现模式; 选择由用户终端支持的资源，根据至少一个呈现模式加载资源，以及生成显示页面。根据本发明，可以实现页面布局多样化，并且可以灵活地在页面中加载各种类型的内容。

28. 发明申请

US20060259882A1 System and method for manipulating an integrated circuit layout 有权
标题翻译：用于操纵集成电路布局的系统和方法
公开(公告)号：US20060259882A1
公开(公告)日：2006-11-16
申请号：US11125168
申请日：2005-05-10
申请人： Po Lin , Yi Su , Miin Shih
发明人： Po Lin , Yi Su , Miin Shih
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating the first virtual device to generate a second symbolic layout. The method further comprises a step of modifying parameters and constraints of the first virtual device to generate a third virtual device, and a step of optimizing a second symbolic layout including the first virtual devices to generate a third symbolic layout based on the third virtual device. Consequently, the second symbolic layout can be reused. Further, the method comprises a step of updating parameters and constraints of the first virtual device based on new process rules to generate a fourth virtual device so that the second symbolic layout can be used to generate a third symbolic layout for migration.
摘要翻译：一种用于操纵允许重用和迁移的集成电路布局的系统和方法。该方法包括以下步骤：识别几何布局中的对象以生成第一符号布局，在第一符号布局中嵌套多个对象以生成第一虚拟设备，以及将第一虚拟设备关联以生成第二符号布局。该方法还包括修改第一虚拟设备的参数和约束以产生第三虚拟设备的步骤，以及优化包括第一虚拟设备的第二符号布局以基于第三虚拟设备生成第三符号布局的步骤。因此，第二个符号布局可以重复使用。此外，该方法包括基于新的过程规则来更新第一虚拟设备的参数和约束以生成第四虚拟设备的步骤，使得可以使用第二符号布局来生成用于迁移的第三符号布局。

29. 发明申请

US20050095790A1 Systems and methods for integration of heterogeneous circuit devices 失效
公开(公告)号：US20050095790A1
公开(公告)日：2005-05-05
申请号：US10990711
申请日：2004-11-17
申请人： Jingkuang Chen , Yi Su
发明人： Jingkuang Chen , Yi Su
IPC分类号： H01L27/14 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L49/00 , H01L21/00
CPC分类号： B81C1/00246 , B81B2201/047 , B81C2203/0735 , H01L21/823493 , H01L21/823892 , H01L21/84 , H01L27/0617 , H01L27/1203
摘要： A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

30. 发明授权

US06658179B2 Monolithic reconfigurable optical multiplexer systems and methods 有权
标题翻译：单片可重构光复用器系统和方法
公开(公告)号：US06658179B2
公开(公告)日：2003-12-02
申请号：US09986395
申请日：2001-11-08
申请人： Joel A. Kubby , Pinyen Lin , Jingkuang Chen , Yi Su
发明人： Joel A. Kubby , Pinyen Lin , Jingkuang Chen , Yi Su
IPC分类号： G02B612
CPC分类号： G02B6/356 , G02B6/12021 , G02B6/12033 , G02B6/2938 , G02B6/3508 , G02B6/3512 , G02B6/3584 , G02B6/3596 , G02B2006/12061 , G02B2006/12097 , G02B2006/12107 , G02B2006/12145 , G02B2006/12164
摘要： A silicon demultiplexer, a plurality of silicon switches and a silicon multiplexer are monolithically integrated on a single silicon chip. In embodiments, the silicon demultiplexer and the silicon multiplexer each comprise a diffraction grating. In other embodiments, the silicon demultiplexer and the silicon multiplexer each comprise an arrayed waveguide grating. In various exemplary embodiments, the silicon optical switches comprise optical switches, micromachined torsion mirrors, electrostatic micromirrors, and/or tilting micromirrors. In use, an optical signal comprising a multiplexed data stream is input into the monolithic reconfigurable optical multiplexer. An optical signal that comprises a modified multiplexed data stream may be output. In an optical communications system, the silicon demultiplexer communicates with an input optical fiber, the plurality of silicon optical switches communicate between the silicon demultiplexer and the silicon multiplexer, and the silicon multiplexer communicates with an output optical fiber. In various embodiments, the optical switches are fabricated to be self-aligned.
摘要翻译：硅解复用器，多个硅开关和硅多路复用器单片集成在单个硅芯片上。在实施例中，硅解复用器和硅多路复用器各自包括衍射光栅。在其他实施例中，硅解复用器和硅多路复用器均包括阵列波导光栅。在各种示例性实施例中，硅光开关包括光开关，微机械扭转镜，静电微镜和/或倾斜微镜。在使用中，包括复用数据流的光信号被输入到单片可重构光复用器。可以输出包括修改的多路复用数据流的光信号。在光通信系统中，硅解复用器与输入光纤通信，多个硅光开关在硅解复用器和硅多路复用器之间通信，并且硅复用器与输出光纤通信。在各种实施例中，光开关被制造成自对准。

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