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21. 发明申请

US20090131602A1 Polyglycolic Acid Resin Particle Composition and Process for Production Thereof 有权
标题翻译：聚乙醇酸树脂颗粒组合物及其制备方法
公开(公告)号：US20090131602A1
公开(公告)日：2009-05-21
申请号：US12084051
申请日：2006-10-26
申请人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
发明人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
IPC分类号： C08G63/06
CPC分类号： C08L67/04 , C08G63/08 , C08G63/912 , C08G2140/00 , C08L2205/02 , Y10T428/2982 , C08L2666/18
摘要： A particulate polyglycolic acid resin composition, comprising: a blend of a first particulate polyglycolic acid resin and a second particulate polyglycolic acid resin each having a moisture content of at most 110 ppm and providing a ratio of melt-viscosity (as measured at 270° C. and a shear rate of 121 sec−1; the same as hereinafter) therebetween of above 1 and at most 10. After the polymerization, the first and second particulate polyglycolic acid resins can cause change in properties before the forming (e.g., during storage); or during the forming process. However, by adequately determining the blending ratio between the resins while taking the melt-viscosities thereof into account, it becomes possible to provide a particulate polyglycolic acid resin composition showing a stable melt-formability and suitable as a starting material for various forming processes.
摘要翻译：一种颗粒状聚乙醇酸树脂组合物，其包含：第一颗粒聚乙醇酸树脂和第二颗粒状聚乙醇酸树脂的共混物，所述第二颗粒聚乙醇酸树脂的水分含量为至多110ppm，并且提供熔体粘度（在270℃下测量），剪切速率为121秒-1，下文相同）在1以上至10以下。聚合后，第一和第二颗粒状聚乙醇酸树脂在成型前会导致性能变化（例如，在储存期间）; 或在成型过程中。然而，通过充分确定树脂之间的共混比，同时考虑其熔融粘度，可以提供显示出稳定的熔融成型性的颗粒聚乙醇酸树脂组合物，并且适合作为各种成型方法的原料。

22. 发明授权

US07728100B2 Process for producing polyglycolic acid resin composition 失效
标题翻译：聚乙醇酸树脂组合物的制备方法
公开(公告)号：US07728100B2
公开(公告)日：2010-06-01
申请号：US11992163
申请日：2006-09-20
申请人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
发明人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
IPC分类号： C08G63/02 , C08G63/00
CPC分类号： C08G63/06 , C08G63/89 , C08G63/90 , C08K5/005 , C08K5/29
摘要： A particulate polyglycolic acid resin composition suitable as a material for various forming processes in produced through a process characterized by comprising: cooling a polyglycolic acid resin composition having a residual glycolide content of at most 0.6 wt. % in a molten state by contact with an aqueous cooling medium to solidify the composition, and pelletizing the composition.
摘要翻译：一种适合作为各种成型方法的材料的颗粒状聚乙醇酸树脂组合物，其特征在于包括：冷却残余乙交酯含量为0.6重量％以下的聚乙醇酸树脂组合物。％的熔融状态通过与水性冷却介质接触固化组合物，并造粒组合物。

23. 发明申请

US20090171039A1 Polyglycolic Acid Resin Composition 有权
标题翻译：聚乙醇酸树脂组合物
公开(公告)号：US20090171039A1
公开(公告)日：2009-07-02
申请号：US12085566
申请日：2006-11-30
申请人： Hiroyuki Sato , Fumio Akutsu , Fuminori Kobayashi
发明人： Hiroyuki Sato , Fumio Akutsu , Fuminori Kobayashi
IPC分类号： C08G63/02
CPC分类号： C08J5/18 , C08J2367/04 , C08K5/25 , C08K5/29 , C08L67/04
摘要： A polyglycolic acid resin composition having improved moisture resistance is obtained by adding a carboxyl group-capping agent and a polymerization catalyst-deactivation agent to a polyglycolic acid resin.
摘要翻译：通过在聚乙醇酸树脂中加入羧基封端剂和聚合催化剂失活剂，得到耐湿性提高的聚乙醇酸树脂组合物。

24. 发明申请

US20090118462A1 Process for Producing Polyglycolic Acid Resin Composition 失效
标题翻译：生产聚乙醇酸树脂组合物的方法
公开(公告)号：US20090118462A1
公开(公告)日：2009-05-07
申请号：US11992163
申请日：2006-09-20
申请人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
发明人： Hiroyuki Sato , Fuminori Kobayashi , Fumio Akutsu , Katsushi Momose
IPC分类号： C08G63/06 , B29B9/00
CPC分类号： C08G63/06 , C08G63/89 , C08G63/90 , C08K5/005 , C08K5/29
摘要： A particulate polyglycolic acid resin composition suitable as a material for various forming processes in produced through a process characterized by comprising: cooling a polyglycolic acid resin composition having a residual glycolide content of at most 0.6 wt. % in a molten state by contact with an aqueous cooling medium to solidify the composition, and pelletizing the composition.
摘要翻译：一种适合作为各种成型方法的材料的颗粒状聚乙醇酸树脂组合物，其特征在于包括：冷却残余乙交酯含量为0.6重量％以下的聚乙醇酸树脂组合物。％的熔融状态通过与水性冷却介质接触固化组合物，并造粒组合物。

25. 发明申请

US20100002551A1 Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof 有权
标题翻译：用于光可重构门阵列的重配置控制装置及其方法
公开(公告)号：US20100002551A1
公开(公告)日：2010-01-07
申请号：US12310487
申请日：2007-08-01
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G11B20/00 , G11B7/00
CPC分类号： H03K19/173
摘要： To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array (1) for producing a laser beam (1a) to serve as a reproducing beam and applying the laser beam (1a), a hologram memory (2) for outputting an optical pattern (2a) when receiving the laser beam (1a) according to pre-stored recording information and outputting a control signal light (2b) relating to optical reconfiguration by the optical pattern (2a), an optically reconfigurable gate array (3) for reconfiguring arrayed logical operation cells into various logical operation circuits according to the outputted optical pattern (2a), and outputting an optical control signal (S3) from the control signal light (2b), and a reproduction light application control means (4) for controlling the application of the laser beam (1a) emitted from the laser array (1) according to the optical control signal. Therefore, optical pattern application can be performed according to the optical control signal at a reconfiguration time adapted to any of various logical operation circuits sequentially reconfigured by the optically reconfigurable gate array. Consequently, correct and reliable write of any one of various types of logical operation circuits can be performed without any write error, and such various types of logical operation circuits can perform logical operation sequentially at high speed.
摘要翻译：提供光学可重构门阵列的重新配置控制器，用于正确可靠地写入光学可重构门阵列的各种类型的逻辑运算电路，并通过快速启动电路来执行高速逻辑运算。解决问题的手段重新配置控制器包括用于产生激光束（1a）以用作再现光束并施加激光束（1a）的激光阵列（1），用于输出光学图案的全息存储器（2）（2a），当根据预先存储的记录信息接收激光束（1a）并且输出与所述光学图案（2a）相关的光学重新配置的控制信号光（2b）时，用于重配置的光学可重构门阵列（3）根据输出的光学图案（2a）将逻辑运算单元转换成各种逻辑运算电路，并从控制信号光（2b）输出光控制信号（S3）;以及再现光应用控制单元（4），用于控制应用根据光学控制信号从激光阵列（1）发射的激光束（1a）。因此，可以根据光控制信号，在适于由光学可重构门阵列顺序重新配置的各种逻辑运算电路中的任何一个的重新配置时间执行光学图案应用。因此，可以执行各种类型的逻辑运算电路中的任一种的正确可靠的写入而没有任何写入错误，并且这种各种类型的逻辑运算电路可以高速顺序地执行逻辑运算。

26. 发明授权

US08054670B2 Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof 有权
标题翻译：用于光可重构门阵列的重配置控制装置及其方法
公开(公告)号：US08054670B2
公开(公告)日：2011-11-08
申请号：US12310487
申请日：2007-08-01
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G11C13/04
CPC分类号： H03K19/173
摘要： [PROBLEMS] To provide a reconfiguration controller of an optically reconfigurable gate array for correctly and reliably writing various types of logical operation circuits of an optically reconfigurable gate array and performing high-speed logical operation by quickly starting up the circuits. [MEANS FOR SOLVING PROBLEMS] A reconfiguration controller comprises a laser array (1) for producing a laser beam (1a) to serve as a reproducing beam and applying the laser beam (1a), a hologram memory (2) for outputting an optical pattern (2a) when receiving the laser beam (1a) according to pre-stored recording information and outputting a control signal light (2b) relating to optical reconfiguration by the optical pattern (2a), an optically reconfigurable gate array (3) for reconfiguring arrayed logical operation cells into various logical operation circuits according to the outputted optical pattern (2a), and outputting an optical control signal (S3) from the control signal light (2b), and a reproduction light application control means (4) for controlling the application of the laser beam (1a) emitted from the laser array (1) according to the optical control signal. Therefore, optical pattern application can be performed according to the optical control signal at a reconfiguration time adapted to any of various logical operation circuits sequentially reconfigured by the optically reconfigurable gate array. Consequently, correct and reliable write of any one of various types of logical operation circuits can be performed without any write error, and such various types of logical operation circuits can perform logical operation sequentially at high speed.
摘要翻译：提供一种光学可重构门阵列的重新配置控制器，用于正确且可靠地写入光学可重构门阵列的各种类型的逻辑运算电路，并通过快速启动电路来执行高速逻辑运算。解决问题的手段重新配置控制器包括用于产生激光束（1a）以用作再现光束并施加激光束（1a）的激光阵列（1），用于输出光学图案的全息存储器（2）（2a），当根据预先存储的记录信息接收激光束（1a）并且输出与所述光学图案（2a）相关的光学重新配置的控制信号光（2b）时，用于重配置的光学可重构门阵列（3）根据输出的光学图案（2a）将逻辑运算单元转换成各种逻辑运算电路，并从控制信号光（2b）输出光控制信号（S3）;以及再现光应用控制单元（4），用于控制应用根据光学控制信号从激光阵列（1）发射的激光束（1a）。因此，可以根据光控制信号，在适于由光学可重构门阵列顺序重新配置的各种逻辑运算电路中的任何一个的重新配置时间执行光学图案应用。因此，可以执行各种类型的逻辑运算电路中的任一种的正确可靠的写入而没有任何写入错误，并且这种各种类型的逻辑运算电路可以高速顺序地执行逻辑运算。

27. 发明申请

US20090296178A1 Optically reconfigurable logic circuit 有权
标题翻译：光学可重构逻辑电路
公开(公告)号：US20090296178A1
公开(公告)日：2009-12-03
申请号：US11597474
申请日：2005-05-11
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： G02F3/00
CPC分类号： H03K19/17748 , H01L27/1446
摘要： To provide an optically reconfigurable logic circuit in which a mount area of an optical circuit is reduced as much as possible and a high gate density is realized.In an optically reconfigurable logic circuit 1 provided with a plurality of configuration information input circuits 6 for converting an optical signal including logic circuit configuration information into an electric signal and holding and outputting this electric signal and a logic configuration variable circuit 7 for performing logic configuration on the basis of the logic circuit configuration information, the configuration information input circuits 6 holds the logic circuit configuration information as electric charge with use of a junction capacitance and a floating capacitance of a photoconductive device P. An inter-terminal voltage of the photoconductive device P is converted into binary data by a binary circuit and output as a circuit configuration signal. Then, the logic configuration variable circuit 7 is configured to execute a logic arithmetic processing before the inter-terminal voltage of the photoconductive device P drops to be equal to or lower than a logic threshold of the binary circuit due to a leak current.
摘要翻译：提供光可重构逻辑电路，其中尽可能减少光电路的安装面积并实现高栅极密度。在具有多个配置信息输入电路6的光学可重构逻辑电路1中，用于将包括逻辑电路配置信息的光信号转换为电信号并保持并输出该电信号，以及用于执行逻辑配置的逻辑配置可变电路7 在逻辑电路配置信息的基础上，配置信息输入电路6使用结电容和感光体P的浮动电容将逻辑电路配置信息保持为电荷。光导器件P的端子间电压通过二进制电路转换成二进制数据并作为电路配置信号输出。然后，逻辑配置可变电路7被配置为在光电导器件P的端子间电压下降到等于或低于由于泄漏电流引起的二进制电路的逻辑阈值之前执行逻辑运算处理。

28. 发明授权

US07508234B2 Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array 有权
标题翻译：光学可重构门阵列写状态检查方法，写状态检测装置和光可重构门阵列
公开(公告)号：US07508234B2
公开(公告)日：2009-03-24
申请号：US11629750
申请日：2005-06-16
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： H01L25/00 , H03K19/177 , H03K17/693
CPC分类号： H03K19/17748 , G01R31/31728 , G01R31/318516
摘要： A technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a local circuit in an ORGA. Upon switching an optical signal to be irradiated on an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit structure of the ORGA, first and second optical signal patterns having the optical signal ON/OFF to be irradiated to the optically reconfigurable bit element serving as optical signal patterns configuring the logical structure in which at least one logical level or output impedance changes are sequentially irradiated and input to the logical circuit. In addition, an output-state detection circuit that is connected to the logical output terminals and detects whether the logical level of the output terminal is at an H level, L level, or high impedance detects the output state.
摘要翻译：用于检查写入状态的技术，而不需要用于ORGA中本地电路的写入状态检查的专用电路。在将要照射在作为检查对象的光学可重构位元件的光信号从ON切换到OFF时，在ORGA的逻辑电路结构中，将具有光信号ON / OFF的第一和第二光信号图案照射到用作构成其中至少一个逻辑电平或输出阻抗改变的逻辑结构的光信号模式的光可重构位元件被顺序照射并输入到逻辑电路。另外，输出状态检测电路与逻辑输出端子连接，检测输出端子的逻辑电平是否为H电平，L电平或高阻抗，检测输出状态。

29. 发明申请

US20080030225A1 Optically Reconfigurable Gate Array Write State Inspection Method, Write State Inspection Device, and Optically Reconfigurable Gate Array 有权
标题翻译：光学可重构门阵列写状态检测方法，写状态检测装置和光可重构门阵列
公开(公告)号：US20080030225A1
公开(公告)日：2008-02-07
申请号：US11629750
申请日：2005-06-16
申请人： Minoru Watanabe , Fuminori Kobayashi
发明人： Minoru Watanabe , Fuminori Kobayashi
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G01R31/31728 , G01R31/318516
摘要： To provide a technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a logical circuit in an ORGA. Upon switching an optical signal to be irradiated an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit structure of the ORGA, first and second optical signal patterns having the optical signal ON/OFF to be irradiated to the optically reconfigurable bit element serving as optical signal patterns configuring the logical structure in which at least one logical level or output impedance changes are sequentially irradiated and input to the logical circuit. In addition, an output-state detection circuit that is connected to the logical output terminals and detects whether the logical level of the output terminal is at eh H level, L level, or high impedance detects the output state. By comparing the detected state with the normal output state of the input optical signal pattern, it is judged whether the information write state of the optically reconfigurable bit element with the optical signal is successful or unsuccessful.
摘要翻译：提供用于检查写入状态的技术，而不需要用于ORGA中的逻辑电路的写入状态检查的专用电路。在将要被照射的光信号作为检查对象从ON切换到OFF时，在ORGA的逻辑电路结构中，将具有光信号ON / OFF的第一和第二光信号图案照射到光学可配置的位元素用作配置至少一个逻辑电平或输出阻抗改变的逻辑结构的光信号模式，并顺序地照射并输入到逻辑电路。另外，连接到逻辑输出端子并检测输出端子的逻辑电平是否处于eh H电平，L电平或高阻抗的输出状态检测电路检测输出状态。通过将检测到的状态与输入光信号图案的正常输出状态进行比较，判断光学可重构位元件与光信号的信息写入状态是成功还是不成功。

30. 发明授权

US6104888A System for determining a characteristic of an image forming unit detachably mounted in an image forming apparatus 有权
标题翻译：用于确定可拆卸地安装在图像形成装置中的图像形成单元的特性的系统
公开(公告)号：US6104888A
公开(公告)日：2000-08-15
申请号：US189766
申请日：1998-11-10
申请人： Fuminori Kobayashi
发明人： Fuminori Kobayashi
IPC分类号： G03G21/00 , G03G21/16 , G03G21/18 , G03G15/00
CPC分类号： G03G21/1875 , G03G2221/1892
摘要： A unit detector 100 includes a main circuit 72 in an image forming device and a complementary circuit 74 in a image forming unit detachably mounted in the image forming device. The complementary circuit 74 has a fuse RF and a first resistor R1, connected in parallel to each other. The main circuit 72 includes a power supply 78, a first circuit portion 82 having a second resistor R2 which is connected through the complementary circuit 74 to the power supply 78 when the unit is properly mounted in the image forming device, and a second circuit portion 84 connected in parallel with the second resistor R2 and having third resistor R4 and switch Tr connected in serial with the resistor R4. The main circuit 72 further includes a detector 88 for detecting a voltage or a current at a portion of the first circuit portion 82. Also mounted in the main circuit 72 is a fusing circuit portion element for closing the switch for a predetermined time for blowing the fuse when it is determined that the fuse has not been blown from the voltage or current detected by the detector 88.
摘要翻译：单元检测器100包括图像形成装置中的主电路72和可拆卸地安装在图像形成装置中的图像形成单元中的互补电路74。互补电路74具有彼此并联连接的熔丝RF和第一电阻器R1。主电路72包括电源78，第一电路部分82，具有第二电阻器R2，当第一电路部分82正确地安装在图像形成装置中时，第二电阻器R2通过互补电路74连接到电源78;第二电路部分 84与第二电阻器R2并联连接并且具有与电阻器R4串联连接的第三电阻器R4和开关Tr。主电路72还包括用于检测第一电路部分82的一部分处的电压或电流的检测器88.还安装在主电路72中的是用于将开关闭合预定时间以用于吹送当确定保险丝没有被检测器88检测到的电压或电流吹过时熔断。

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