专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08436415B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08436415B2
公开(公告)日：2013-05-07
申请号：US12723981
申请日：2010-03-15
申请人： Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792
CPC分类号： H01L29/66833 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.
摘要翻译：存储器串包括：第一半导体层，包括在基板上沿堆叠方向延伸的柱状部分; 围绕所述柱状部分的第一电荷存储层; 以及堆叠在所述基板上以围绕所述第一电荷存储层的多个第一导电层。选择晶体管包括：与柱状部分的上表面接触并沿堆叠方向延伸的第二半导体层; 围绕所述第二半导体层的第二电荷存储层; 以及沉积在所述第一导电层上方以围绕所述第二电荷存储层的第二导电层。第二电荷存储层由第二导电层向下的层向第二导电层的上端附近形成，并且不形成在上端附近的上方。

22. 发明申请

US20110013454A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110013454A1
公开(公告)日：2011-01-20
申请号：US12726858
申请日：2010-03-18
申请人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoo Hishida , Yoshihisa Iwata , Megumi Ishiduki , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhel Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C5/025 , G11C5/02 , G11C5/04 , G11C16/0483 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.
摘要翻译：非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。开关电路控制第二线和第一线之间的电连接。

23. 发明申请

US20110051527A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110051527A1
公开(公告)日：2011-03-03
申请号：US12725827
申请日：2010-03-17
申请人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
发明人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
IPC分类号： G11C16/04 , G11C16/02
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
摘要翻译：非易失性半导体存储器件包括：存储器单元; 和控制单元。存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高而不是V3到第二布线，或将第二布线置于浮置状态。

24. 发明授权

US08320182B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08320182B2
公开(公告)日：2012-11-27
申请号：US12725827
申请日：2010-03-17
申请人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
发明人： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
摘要翻译：非易失性半导体存储器件包括：存储器单元; 和控制单元。存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高而不是V3到第二布线，或将第二布线置于浮置状态。

25. 发明授权

US08507972B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08507972B2
公开(公告)日：2013-08-13
申请号：US12821551
申请日：2010-06-23
申请人： Shigeto Oota , Yoshimasa Mikajiri , Masaru Kito , Ryouhei Kirisawa
发明人： Shigeto Oota , Yoshimasa Mikajiri , Masaru Kito , Ryouhei Kirisawa
IPC分类号： H01L29/94
CPC分类号： H01L29/792 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structural unit, a semiconductor pillar, a memory layer, an inner insulating film, an outer insulating film and a cap insulating film. The unit includes a plurality of electrode films stacked alternately in a first direction with a plurality of inter-electrode insulating films. The pillar pierces the stacked structural unit in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and the electrode films. The cap insulating film is provided between the outer insulating film and the electrode films, and the cap insulating film has a higher relative dielectric constant than the outer insulating film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括层叠结构单元，半导体柱，存储层，内绝缘膜，外绝缘膜和帽绝缘膜。该单元包括在多个电极间绝缘膜上沿第一方向交替堆叠的多个电极膜。支柱沿第一方向刺穿层叠的结构单元。存储层设置在电极膜和半导体柱之间。内部绝缘膜设置在存储层和半导体柱之间。外绝缘膜设置在存储层和电极膜之间。帽绝缘膜设置在外绝缘膜和电极膜之间，并且帽绝缘膜具有比外绝缘膜更高的相对介电常数。

26. 发明授权

US08194467B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08194467B2
公开(公告)日：2012-06-05
申请号：US12725742
申请日：2010-03-17
申请人： Yoshimasa Mikajiri , Ryouhei Kirisawa , Masaru Kito , Shigeto Oota
发明人： Yoshimasa Mikajiri , Ryouhei Kirisawa , Masaru Kito , Shigeto Oota
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/0466 , G11C5/02 , G11C16/0483 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.
摘要翻译：非易失性半导体存储器件包括：存储器单元; 和控制单元。存储单元包括：交替堆叠的包括电极膜和电极间绝缘膜的多层结构; 穿透多层结构的半导体柱; 绝缘膜和设置在电极膜和半导体柱之间的存储层; 以及连接到半导体柱的布线。在擦除操作中，控制单元执行以下操作：在第一时段期间将布线设置为第一电位的第一操作和低于第一电位的第二电位的电极膜; 以及在第一操作之后的第二周期期间将布线设置在第三电位的第二操作和电极膜处于低于第三电位的第四电位。第二周期的长度比第一周期短，和/或第三和第四电位之间的差小于第一和第二电位之间的差。

27. 发明申请

US20110216604A1 METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：操作半导体存储器件的方法
公开(公告)号：US20110216604A1
公开(公告)日：2011-09-08
申请号：US13039557
申请日：2011-03-03
申请人： Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
发明人： Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/16 , G11C16/3445 , H01L27/11582
摘要： According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
摘要翻译：根据一个实施例，公开了一种用于操作半导体存储器件的方法。半导体存储器件包括衬底，层叠体，存储膜，通道体，选择晶体管和布线。该方法可以通过向布线，选择栅极和字电极层施加第一擦除电位来提高通道体的电位。此外，在通道体的电位升高之后，在布线和选择栅极保持第一擦除电位的情况下，该方法可以将字电极层的电位降低到低于第一擦除电位的第二擦除电位。

28. 发明授权

US08351277B2 Method for operating semiconductor memory device 有权
标题翻译：操作半导体存储器件的方法
公开(公告)号：US08351277B2
公开(公告)日：2013-01-08
申请号：US13039557
申请日：2011-03-03
申请人： Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
发明人： Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/16 , G11C16/3445 , H01L27/11582
摘要： According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
摘要翻译：根据一个实施例，公开了一种用于操作半导体存储器件的方法。半导体存储器件包括衬底，层叠体，存储膜，通道体，选择晶体管和布线。该方法可以通过向布线，选择栅极和字电极层施加第一擦除电位来提高通道体的电位。此外，在通道体的电位升高之后，在布线和选择栅极保持第一擦除电位的情况下，该方法可以将字电极层的电位降低到低于第一擦除电位的第二擦除电位。

29. 发明申请

US20110063914A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110063914A1
公开(公告)日：2011-03-17
申请号：US12725742
申请日：2010-03-17
申请人： Yoshimasa MIKAJIRI , Ryouhei Kirisawa , Masaru Kito , Shigeto Oota
发明人： Yoshimasa MIKAJIRI , Ryouhei Kirisawa , Masaru Kito , Shigeto Oota
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0466 , G11C5/02 , G11C16/0483 , H01L27/11556 , H01L27/11573 , H01L27/11578
摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials.
摘要翻译：非易失性半导体存储器件包括：存储器单元; 和控制单元。存储单元包括：交替堆叠的包括电极膜和电极间绝缘膜的多层结构; 穿透多层结构的半导体柱; 绝缘膜和设置在电极膜和半导体柱之间的存储层; 以及连接到半导体柱的布线。在擦除操作中，控制单元执行以下操作：在第一时段期间将布线设置为第一电位的第一操作和低于第一电位的第二电位的电极膜; 以及在第一操作之后的第二周期期间将布线设置在第三电位的第二操作和电极膜处于低于第三电位的第四电位。第二周期的长度比第一周期短，和/或第三和第四电位之间的差小于第一和第二电位之间的差。

30. 发明授权

US08581326B2 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08581326B2
公开(公告)日：2013-11-12
申请号：US12727644
申请日：2010-03-19
申请人： Shigeto Oota , Yoshimasa Mikajiri , Ryouhei Kirisawa
发明人： Shigeto Oota , Yoshimasa Mikajiri , Ryouhei Kirisawa
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.
摘要翻译：一种非易失性半导体存储器件，包括：第一层叠体，其具有第一存储单元的多个第一栅电极;第二层叠体，每个第二层叠体具有第二存储单元的多个第二栅电极，位于第一存储单元的侧表面的栅绝缘膜部; 第二层叠体，各自位于第一和第二层叠体之间的第一半导体层，连接到第一存储单元中的最上面的第一选择晶体管，连接到第二存储单元中最上面的第一选择晶体管，隔离绝缘膜将第一和第二选择晶体管分离成第一和第二层叠体侧的部分，以及位于从前表面侧到背面侧穿透隔离绝缘膜并连接到第一半导体层的衬底电位施加电极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式