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21. 发明授权

US08154072B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US08154072B2
公开(公告)日：2012-04-10
申请号：US12403493
申请日：2009-03-13
申请人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
发明人： Masahiro Koike , Yuichiro Mitani , Tatsuo Shimizu , Naoki Yasuda , Yasushi Nakasaki , Akira Nishiyama
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/513
摘要： A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：在半导体层中形成为彼此间隔一定距离的源区和漏区; 形成在位于源极区域和漏极区域之间的半导体层上的第一绝缘膜，所述第一绝缘膜包括形成在所述第一绝缘层上并具有比所述第一绝缘层高的介电常数的第一绝缘层和第二绝缘层所述第二绝缘层具有进行孔捕获和释放的第一部位，所述第一部位通过将不同于基材的元素添加到所述第二绝缘膜而形成，所述第一部位位于比所述第二绝缘膜的费米能级更低的水平形成半导体层的材料; 形成在所述第一绝缘膜上的电荷存储膜; 形成在电荷存储膜上的第二绝缘膜; 以及形成在所述第二绝缘膜上的控制栅电极。

22. 发明授权

US08115261B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08115261B2
公开(公告)日：2012-02-14
申请号：US11790854
申请日：2007-04-27
申请人： Tsunehiro Ino , Yasushi Nakasaki
发明人： Tsunehiro Ino , Yasushi Nakasaki
IPC分类号： H01L29/94
CPC分类号： H01L21/31604 , C23C14/08 , C23C14/5806 , C23C14/5853 , H01L21/02148 , H01L21/02159 , H01L21/02161 , H01L21/02266 , H01L21/02337 , H01L21/02356 , H01L21/28194 , H01L21/28282 , H01L21/31608 , H01L21/31641 , H01L21/31645 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/513 , H01L29/517 , H01L29/7881 , H01L29/792
摘要： It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81≦x≦0.99, 0.04≦y≦0.25, 0≦z≦1) on a semiconductor substrate, the ranges of composition ratios x, y, and z being values measured by XPS; and transforming the amorphous film into an insulating film containing (HfzZr1-z)xSi1-xO2 as tetragonal crystals, by performing annealing at 750° C. or higher on the amorphous film in an atmosphere containing oxygen.
摘要翻译：可以提供具有最高可能的介电常数并且可以以低生产成本制造的半导体器件的半导体器件和制造方法。一种半导体器件的制造方法，其特征在于，在半导体衬底上形成含有（Hf z Zr 1-z）x Si 1-x O 2-y（0.81≤n1E; x＆nlE; 0.99,0.04＆nlE; y＆nlE; 0.25,0＆nlE; z＆nlE; 1），组成比x，y和z的范围是通过XPS测量的值; 并通过在含有氧气的气氛中在非晶膜上进行750℃以上的退火，将非晶质膜变形为含有（Hf z Zr 1-z）x Si 1-x O 2的四方晶体的绝缘膜。

23. 发明授权

US07999303B2 NAND-type nonvolatile semiconductor memory device 有权
标题翻译： NAND型非易失性半导体存储器件
公开(公告)号：US07999303B2
公开(公告)日：2011-08-16
申请号：US12353586
申请日：2009-01-14
申请人： Shoko Kikuchi , Yasushi Nakasaki , Koichi Muraoka
发明人： Shoko Kikuchi , Yasushi Nakasaki , Koichi Muraoka
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide,a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control gate electrode, and a second source/drain region.
摘要翻译：本发明提供一种在选择晶体管中使用氧化铝膜作为栅绝缘膜的一部分的高性能MONOS型NAND型非易失性半导体存储器件，并且作为存储晶体管中的块绝缘膜。 NAND型非易失性半导体存储器件在半导体衬底上具有串联连接的多个存储单元晶体管和选择晶体管。存储单元晶体管包括半导体衬底上的第一绝缘膜，电荷俘获层，由氧化铝制成的第二绝缘膜，第一控制栅极电极和第一源极/漏极区域。选择晶体管包括半导体衬底上的第三绝缘膜，由包含四价阳离子元素，五价阳离子元素和N（氮）中的至少一种的氧化铝制成的第四绝缘膜，第二控制栅电极和第二源极/漏极区域。

24. 发明申请

US20090134479A1 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US20090134479A1
公开(公告)日：2009-05-28
申请号：US12320280
申请日：2009-01-22
申请人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
发明人： Yuuichi Kamimuta , Akira Nishiyama , Yasushi Nakasaki , Tsunehiro Ino , Masato Koyama
IPC分类号： H01L29/78
CPC分类号： H01L27/11521 , H01L21/28194 , H01L21/28202 , H01L29/4933 , H01L29/4975 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.

25. 发明授权

US06054371A Method of manufacturing a semiconductor device by detachably mounting substrates to a holder board 失效
标题翻译：通过将基板可拆卸地安装到保持板来制造半导体器件的方法
公开(公告)号：US06054371A
公开(公告)日：2000-04-25
申请号：US162155
申请日：1998-09-29
申请人： Masakatsu Tsuchiaki , Yasushi Nakasaki , Akira Nishiyama , Yukihito Oowaki , Hirotaka Nishino
发明人： Masakatsu Tsuchiaki , Yasushi Nakasaki , Akira Nishiyama , Yukihito Oowaki , Hirotaka Nishino
IPC分类号： H01L21/762 , H01L21/02 , H01L21/68 , H01L25/04 , H01L25/18 , H01L27/108 , H01L27/12 , H01L21/30 , H01L21/00 , H01L21/44 , H01L21/46 , H01L21/84
CPC分类号： H01L21/6835 , H01L2221/68313 , H01L27/10897 , H01L2924/0002 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： Disclosed is a method of manufacturing a semiconductor device, comprising the step of detachably mounting a plurality of semiconductor substrates to a first holder board so as to form a complex semiconductor substrate, and the step of subjecting the plural semiconductor substrates included in the complex semiconductor substrates to common steps of manufacturing a semiconductor device. At least one of the plural semiconductor substrates is mounted to a second holder board. The particular semiconductor substrate is detached from the second holder board and, then, mounted to the first holder board. Alternatively, at least one of the plural semiconductor substrates is detached from the first holder board and, then, mounted to a third holder board differing in size from the first holder board.
摘要翻译：公开了一种制造半导体器件的方法，包括以下步骤：将多个半导体衬底可拆卸地安装到第一保持器板以形成复合半导体衬底;以及对包含在复合半导体衬底中的多个半导体衬底进行处理的步骤涉及制造半导体器件的常规步骤。多个半导体衬底中的至少一个安装到第二保持器板。特定的半导体衬底从第二保持器板分离，然后安装到第一保持器板。或者，多个半导体衬底中的至少一个从第一保持器板分离，然后安装到尺寸与第一保持器板不同的第三保持器板。

26. 发明申请

US20110266612A1 NAND-TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： NAND型非易失性半导体存储器件
公开(公告)号：US20110266612A1
公开(公告)日：2011-11-03
申请号：US13182283
申请日：2011-07-13
申请人： Shoko KIKUCHI , Yasushi Nakasaki , Koichi Muraoka
发明人： Shoko KIKUCHI , Yasushi Nakasaki , Koichi Muraoka
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/78
摘要： The present invention provides a high-performance MONOS-type NAND-type nonvolatile semiconductor memory device using an aluminum oxide film as a part of gate insulating film in a select transistor and as a block insulating film in a memory transistor. The NAND-type nonvolatile semiconductor memory device has, on a semiconductor substrate, a plurality of memory cell transistors connected to each other in series and a select transistor. The memory cell transistor includes a first insulating film on the semiconductor substrate, a charge trapping layer, a second insulating film made of aluminum oxide, a first control gate electrode, and a first source/drain region. The select transistor includes a third insulating film on the semiconductor substrate, a fourth insulating film made of an aluminum oxide containing at least one of a tetravalent cationic element, a pentavalent cationic element, and N (nitrogen), a second control gate electrode, and a second source/drain region.
摘要翻译：本发明提供一种在选择晶体管中使用氧化铝膜作为栅绝缘膜的一部分的高性能MONOS型NAND型非易失性半导体存储器件，并且作为存储晶体管中的块绝缘膜。 NAND型非易失性半导体存储器件在半导体衬底上具有串联连接的多个存储单元晶体管和选择晶体管。存储单元晶体管包括半导体衬底上的第一绝缘膜，电荷俘获层，由氧化铝制成的第二绝缘膜，第一控制栅极电极和第一源极/漏极区域。选择晶体管包括半导体衬底上的第三绝缘膜，由包含四价阳离子元素，五价阳离子元素和N（氮）中的至少一种的氧化铝制成的第四绝缘膜，第二控制栅电极和第二源极/漏极区域。

27. 发明授权

US08013380B2 Non-volatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08013380B2
公开(公告)日：2011-09-06
申请号：US12212128
申请日：2008-09-17
申请人： Yasushi Nakasaki , Koichi Muraoka , Naoki Yasuda , Shoko Kikuchi
发明人： Yasushi Nakasaki , Koichi Muraoka , Naoki Yasuda , Shoko Kikuchi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , H01L29/513 , H01L29/7881
摘要： A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al2O3.
摘要翻译：一种能够电写入，擦除，读取和保留数据的MONOS型非易失性半导体存储器件，所述存储器件包括源极/漏极区，第一栅极绝缘层，形成在第一栅极绝缘层上的第一电荷俘获层形成在第一电荷俘获层上的第二栅极绝缘层，以及形成在第二栅极绝缘层上的控制电极。第一电荷俘获层包括含有Al和O作为主要元素并且具有由间隙O原子和四价阳离子原子的复合物形成的缺陷对的绝缘膜，代替Al原子，绝缘膜还具有电子未占有的含量从Al2O3的价带最大值测量的2eV-6eV的范围。

28. 发明申请

US20100244157A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100244157A1
公开(公告)日：2010-09-30
申请号：US12710851
申请日：2010-02-23
申请人： Izumi HIRANO , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
发明人： Izumi HIRANO , Yuichiro Mitani , Tatsuo Shimizu , Yasushi Nakasaki , Akiko Masada , Shigeto Fukatsu , Masahiro Koike
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28079 , H01L29/4958 , H01L29/513 , H01L29/518 , H01L29/665 , H01L29/6659
摘要： A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm−3 to 2.96×1020 cm−3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.
摘要翻译：半导体器件包括：MISFET，包括：半导体层，包括形成在其中的半导体区域; 形成在所述半导体区域上方的栅极绝缘膜，并且包括含有金属和氧的金属氧化物层，所述金属氧化物层中所含的金属为选自Hf和Zr中的至少一种，所述金属氧化物层还包含至少一种元素选自Ru，Cr，Os，V，Tc和Nb的金属氧化物层，金属氧化物层具有捕获或释放由元素包含形成的电荷的部位，金属氧化物层中的元素的密度在该范围内 1×1015cm-3至2.96×1020cm-3，这些位置被分配成具有比金属氧化物层的中心更靠近半导体区域的峰; 以及形成在栅极绝缘膜上的栅电极。

29. 发明申请

US20070252232A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070252232A1
公开(公告)日：2007-11-01
申请号：US11790854
申请日：2007-04-27
申请人： Tsunehiro Ino , Yasushi Nakasaki
发明人： Tsunehiro Ino , Yasushi Nakasaki
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L21/31604 , C23C14/08 , C23C14/5806 , C23C14/5853 , H01L21/02148 , H01L21/02159 , H01L21/02161 , H01L21/02266 , H01L21/02337 , H01L21/02356 , H01L21/28194 , H01L21/28282 , H01L21/31608 , H01L21/31641 , H01L21/31645 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/513 , H01L29/517 , H01L29/7881 , H01L29/792
摘要： It is made possible to provide a semiconductor device and a method for manufacturing the semiconductor device that have the highest possible permittivity and can be produced at low production costs. A method for manufacturing a semiconductor device, includes: forming an amorphous film containing (HfzZr1-z)xSi1-xO2-y (0.81≦x≦0.99, 0.04≦y≦0.25, 0≦z≦1) on a semiconductor substrate, the ranges of composition ratios x, y, and z being values measured by XPS; and transforming the amorphous film into an insulating film containing (HfzZr1-z)xSi1-xO2 as tetragonal crystals, by performing annealing at 750° C. or higher on the amorphous film in an atmosphere containing oxygen.
摘要翻译：可以提供具有最高可能的介电常数并且可以以低生产成本制造的半导体器件的半导体器件和制造方法。一种半导体器件的制造方法，包括：形成含有（Hf z z z 1 z z）x Si 1的非晶膜在半导体衬底上的-x 2-y（0.81 <= x <= 0.99,0.04 <= y <= 0.25,0 <= z <= 1）组成比x，y和z是通过XPS测量的值; 以及将所述非晶膜转变成含有（Hf z z 1 z z）x Si 1 x x的绝缘膜 > O 2作为四方晶体，通过在含氧的气氛中在非晶膜上在750℃以上进行退火。

30. 发明授权

US06689284B1 Surface treating method 失效
标题翻译：表面处理方法
公开(公告)号：US06689284B1
公开(公告)日：2004-02-10
申请号：US09672018
申请日：2000-09-29
申请人： Yasushi Nakasaki
发明人： Yasushi Nakasaki
IPC分类号： B05D724
CPC分类号： B08B7/00 , B08B3/00
摘要： A method is provided for surface treating where the environmental load is small. The surface treating method includes a cluster produced in a gas phase and bonded by a first molecule and a second molecule by means of an intermolecular force. At least a part of the internal energy released in producing the cluster is utilized whereby the first molecule contained in the cluster has a higher reactivity than that of the first molecule that is not bonded to the second molecule. The surface of the member to be treated is treated in a gas phase with the cluster containing the first molecule having a higher reactivity.
摘要翻译：在环境负荷小的地方进行表面处理的方法。表面处理方法包括以气相形成的并通过分子间力与第一分子和第二分子结合的簇。使用在产生簇中释放的内部能量的至少一部分，其中包含在簇中的第一分子具有比未结合到第二分子的第一分子的反应性更高的反应性。要处理的构件的表面在气相中处理，其中包含具有较高反应性的第一分子的簇。

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