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21. 发明授权

US07636287B2 Reproduced signal equalizing method for optical information media and optical information reproducing/recording apparatus 失效
标题翻译：用于光信息介质和光信息再现/记录装置的再现信号均衡方法
公开(公告)号：US07636287B2
公开(公告)日：2009-12-22
申请号：US10822374
申请日：2004-04-12
申请人： Shuichi Ohkubo , Hiromi Honma , Masatsugu Ogawa , Masaki Nakano , Toshiaki Iwanaga , Yutaka Kashihara , Yuji Nagai , Akihito Ogawa
发明人： Shuichi Ohkubo , Hiromi Honma , Masatsugu Ogawa , Masaki Nakano , Toshiaki Iwanaga , Yutaka Kashihara , Yuji Nagai , Akihito Ogawa
IPC分类号： G11B7/005 , G11B7/00
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/1012 , G11B20/10296 , G11B20/10481 , G11B2020/1288 , G11B2220/2541
摘要： Reproduced signals are equalized by the least square technique by using a predetermined number of data samples binarized by a Viterbi decoder. Even when data written on an optical disk is unknown, the data can be equalized in a stable manner and can be reproduced at a low error rate without instability factors such as divergence due to interference.
摘要翻译：通过使用由维特比解码器二值化的预定数量的数据样本，通过最小二乘法来再现信号。即使在光盘上写入的数据未知的情况下，数据也可以以稳定的方式进行均衡，并且能够以低错误率再现，而不会引起由于干扰引起的发散等不稳定因素。

22. 发明授权

US06928125B2 Recording state detection system for use in a disk drive 失效
标题翻译：用于磁盘驱动器的记录状态检测系统
公开(公告)号：US06928125B2
公开(公告)日：2005-08-09
申请号：US10027737
申请日：2001-12-21
申请人： Masaki Nakano , Hiromi Honma , Masaki Hidano
发明人： Masaki Nakano , Hiromi Honma , Masaki Hidano
IPC分类号： G11B20/10 , G11B7/0045 , G11B20/18 , H04L1/00 , H03D1/00
CPC分类号： G11B20/1816 , G11B20/10296
摘要： A recording state detection system includes a Viterbi detection unit, an error calculation unit for calculating error data series representing a difference between each sample data of the reproduced data series and a corresponding data of the data series output from the Viterbi detection unit, a normal level judgement unit for judging the normal level of each sample data, and a state calculation unit for calculating the amplitude data and the asymmetry of the sample data series based on the error data series and the normal level. The disk drive unit corrects a recording optical power based on the calculated amplitude and the asymmetry.
摘要翻译：记录状态检测系统包括维特比检测单元，误差计算单元，用于计算表示再现数据序列的每个采样数据与维特比检测单元输出的数据序列的相应数据之间的差异的误差数据序列，正常水平用于判断每个样本数据的正常水平的判断单元，以及用于基于误差数据序列和正常水平计算样本数据序列的幅度数据和不对称性的状态计算单元。磁盘驱动器单元根据计算的振幅和不对称来校正记录光功率。

23. 发明授权

US5920533A Clock signal extraction system for high density recording apparatus 失效
标题翻译：用于高密度记录装置的时钟信号提取系统
公开(公告)号：US5920533A
公开(公告)日：1999-07-06
申请号：US653760
申请日：1996-05-23
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： G11B7/00 , G11B7/005 , G11B20/10 , G11B20/14
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/10296 , G11B20/1403
摘要： The invention provides a clock signal extraction circuit which can extract a synchronizing clock signal accurately from a readout waveform reproduced from information recorded in a high density and which includes substantial intersymbol interferences. An analog readout signal is converted into binary information with a synchronizing clock signal from a voltage controlled oscillator. A replica signal is produced from the binary information by a waveform replica production circuit while time corrected readout waveform data are produced from the analog readout signal by a delay circuit, and a phase amount is detected from the time corrected readout waveform data and the replica signal by a phase amount detection circuit. The base amount is used to control the voltage controlled oscillator, thereby forming a phase locked loop to perform a follow-up operation to the readout signal.
摘要翻译：本发明提供了一种时钟信号提取电路，其可以从从高密度记录的信息再现的读出波形中精确地提取同步时钟信号，并且包括实质的符号间干扰。模拟读出信号由来自压控振荡器的同步时钟信号转换为二进制信息。通过波形复制品生成电路从二进制信息产生复制信号，同时通过延迟电路从模拟读出信号产生时间校正的读出波形数据，并且从时间校正的读出波形数据和复制信号中检测相位量通过相位量检测电路。基本量用于控制压控振荡器，从而形成锁相环以对读出信号执行后续操作。

24. 发明授权

US08693296B2 PLL circuit and disk drive 失效
标题翻译： PLL电路和磁盘驱动器
公开(公告)号：US08693296B2
公开(公告)日：2014-04-08
申请号：US12519691
申请日：2007-12-04
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： G11B7/00
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B20/14 , G11B2020/1239 , G11B2020/1244 , G11B2020/1245 , G11B2220/2537 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.
摘要翻译：数字环路滤波器接收从相位比较器输出的相位误差，以产生数字频率值。该数字频率值由D / A转换器转换为模拟电压，VCO输出与D / A转换器输出的电压对应的频率同步基座。来自相位比较器的相位误差输出由数字环路滤波器的输出与特定系数“A”的乘积进行增益校正，并传送到数字环路滤波器。输入到数字环路滤波器的相位误差与输出时钟频率成比例地变化，由此PLL环路根据输出时钟频率线性地控制环路特性。

25. 发明授权

US08456977B2 Digital PLL circuit, information readout device, disc readout device, and signal processing method 有权
标题翻译：数字PLL电路，信息读出装置，光盘读出装置及信号处理方法
公开(公告)号：US08456977B2
公开(公告)日：2013-06-04
申请号：US13137967
申请日：2011-09-22
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： G11B7/00
CPC分类号： G11B20/1025 , G11B20/10046 , G11B2220/2562 , H03D2200/0086
摘要： A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.
摘要翻译：数字PLL（锁相环）电路（及其方法）包括基于给定截止频率来限制输入RF（射频）信号的频率带宽的AAF（抗混叠滤波器），ADC（模拟数字转换器），其基于给定的采样频率对转换器的数据速率的下变频器进行采样，以及数字相位跟踪单元，该单位从ADC的输出信号产生同步时钟信号，基于给定内部频率的下变频器。即使当RF信号的频率带宽波动时，截止频率和采样频率分别是固定的。降压转换器根据RF信号的频率带宽的增加来降低数据速率。

26. 发明申请

US20120087225A1 Digital PLL circuit, information readout device, disc readout device, and signal processing method 有权
标题翻译：数字PLL电路，信息读出装置，光盘读出装置及信号处理方法
公开(公告)号：US20120087225A1
公开(公告)日：2012-04-12
申请号：US13137967
申请日：2011-09-22
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： H03L7/06 , G11B20/10 , H03D3/24
CPC分类号： G11B20/1025 , G11B20/10046 , G11B2220/2562 , H03D2200/0086
摘要： A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.
摘要翻译：数字PLL（锁相环）电路（及其方法）包括基于给定截止频率来限制输入RF（射频）信号的频率带宽的AAF（抗混叠滤波器），ADC（模拟数字转换器），其基于给定的采样频率对转换器的数据速率的下变频器进行采样，以及数字相位跟踪单元，该单位从ADC的输出信号产生同步时钟信号，基于给定内部频率的下变频器。即使当RF信号的频率带宽波动时，截止频率和采样频率分别是固定的。降压转换器根据RF信号的频率带宽的增加来降低数据速率。

27. 发明授权

US08004443B2 Information readout apparatus and information reproducing method 失效
标题翻译：信息读取装置和信息再现方法
公开(公告)号：US08004443B2
公开(公告)日：2011-08-23
申请号：US12524072
申请日：2008-01-07
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： H03M1/12
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10055 , G11B20/10111 , G11B20/10212 , G11B20/10296 , G11B20/10425 , G11B20/10481 , G11B20/1403 , G11B20/1426 , G11B2220/2562
摘要： An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency. The maximum likelihood detecting means converts the output data outputted from said interpolation means into an M-bit detection data, and outputs said detection data in synchronous with said second clock signal signal. The PLL means generates said first clock signal and said second clock signal based on said read signal.
摘要翻译：信息读取装置包括模数转换装置，均衡装置，内插装置，最大似然检测装置和PLL装置。模数转换装置将从最短游程长度为1的游程长度限制码记录有数据的光盘介质读出的读取信号转换成数字信号，并与数字信号同步输出第一时钟信号，其频率是信道频率的N / M倍。此时，N是等于或大于2的整数，M是满足N / M> 0.5的整数。均衡装置将所述数字信号与所述第一时钟信号信号同步地将先前指定的部分响应（PR）特性相等。内插装置将从所述均衡装置输出的N个输入数据转换为M个输出数据，并以与信道频率的1 / M倍的频率的第二时钟信号同步地输出输出数据。最大似然检测装置将从所述插值装置输出的输出数据转换成M位检测数据，并且与所述第二时钟信号信号同步地输出所述检测数据。 PLL装置基于所述读取信号产生所述第一时钟信号和所述第二时钟信号。

28. 发明申请

US20100091624A1 Information reproducing device 失效
标题翻译：信息再生装置
公开(公告)号：US20100091624A1
公开(公告)日：2010-04-15
申请号：US12448533
申请日：2007-12-11
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： G11B23/00
CPC分类号： H03L7/08 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10055 , G11B20/10222 , G11B2220/2537 , H03L2207/50
摘要： An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.
摘要翻译： A / D转换器与具有固定频率的系统时钟sclk同步地对读取信号进行采样，以执行A / D转换。波动补偿器被配置为内部反馈型补偿滤波器，并且抑制从A / D转换器输出的数字信号的波动。数字PLL使用内插器以与通道频率同步的定时通过内插生成读取信号的采样值，并且使用NCO来产生反馈到内插器的同步时钟和内插相位信号。二值化电路基于从内插器输出的内插值二值化读取信号。基于从环路滤波器输出的频率值来控制波动补偿器的频率特性。

29. 发明授权

US07091895B2 A/D converter, digital PLL circuit using the same, and information recording apparatus using the same 有权
标题翻译： A / D转换器，使用该数字PLL电路的数字PLL电路以及使用其的信息记录装置
公开(公告)号：US07091895B2
公开(公告)日：2006-08-15
申请号：US10957385
申请日：2004-10-01
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： H03M1/00
CPC分类号： G11B20/1403 , G11B2020/1239 , H03L7/0807 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/361
摘要： An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.
摘要翻译： A / D转换器包括将输入信号转换为4位或更小的数字值的低位分辨率A / D，以及抑制来自该位置的输出中的高频带分量的低通数字滤波器低位分辨率A / D，并且将包含在输入信号中的相位信息提取为振幅信息。还公开了数字PLL电路和信息记录装置。

30. 发明申请

US20050073454A1 A/D converter, digital PLL circuit using the same, and information recording apparatus using the same 有权
标题翻译： A / D转换器，使用该数字PLL电路的数字PLL电路以及使用其的信息记录装置
公开(公告)号：US20050073454A1
公开(公告)日：2005-04-07
申请号：US10957385
申请日：2004-10-01
申请人： Hiromi Honma
发明人： Hiromi Honma
IPC分类号： G11B20/10 , H03L7/08 , H03L7/091 , H03L7/099 , H03M1/36 , H03M1/64 , H03M1/12
CPC分类号： G11B20/1403 , G11B2020/1239 , H03L7/0807 , H03L7/091 , H03L7/0991 , H03L2207/50 , H03M1/361
摘要： An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.
摘要翻译： A / D转换器包括将输入信号转换为4位或更小的数字值的低位分辨率A / D，以及抑制来自该位置的输出中的高频带分量的低通数字滤波器低位分辨率A / D，并且将包含在输入信号中的相位信息提取为振幅信息。还公开了数字PLL电路和信息记录装置。

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