会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 28. 发明授权
    • Nonaqueous electrolyte secondary battery
    • 非水电解质二次电池
    • US08021782B2
    • 2011-09-20
    • US12397467
    • 2009-03-04
    • Shinya MiyazakiTatsuyuki Kuwahara
    • Shinya MiyazakiTatsuyuki Kuwahara
    • H01M4/48
    • H01M4/131H01M4/1391H01M4/485H01M4/505H01M4/525H01M10/0525H01M2004/028
    • The present invention provides a nonaqueous electrolyte secondary battery with an excellent packing property and remarkably improved high-temperature cycle characteristics and thermal stability. The nonaqueous electrolyte secondary battery 10 includes a positive electrode plate 11 having a positive electrode active material able to absorb and desorb lithium ions, a negative electrode plate having a negative electrode active material capable of absorption and desorption of lithium ions, and a nonaqueous electrolyte, and the positive electrode active material includes a mixture of material A: LiwNixCoyMnzO2 (where 1.00≦w≦1.30, x+y+z=1, 0.40≦x≦0.50, and 0.30≦y≦0.40) and material B: LiwNixCoyMnzO2 (where 1.00≦w≦1.30, x+y+z=1, 0.30≦x≦0.35, and 0.30≦y≦0.35).
    • 本发明提供一种具有优异的包装性能和显着提高的高温循环特性和热稳定性的非水电解质二次电池。 非水电解质二次电池10包括具有能够吸收和解吸锂离子的正极活性物质的正极板11,具有能够吸收和解吸锂离子的负极活性物质的负极板和非水电解质, 正极活性物质包括材料A:LiwNixCoyMnzO2(其中1.00≦̸ w≦̸ 1.30,x + y + z = 1,0.40& nl; x< lE; 0.50和0.30≦̸ y≦̸ 0.40)和材料B: LiwNixCoyMnzO2(其中1.00≦̸ w≦̸ 1.30,x + y + z = 1,0.30≦̸ x≦̸ 0.35和0.30≦̸ y≦̸ 0.35)。
    • 30. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07116571B2
    • 2006-10-03
    • US10505216
    • 2002-02-20
    • Shinya MiyazakiKei KatohKoudoh Yamauchi
    • Shinya MiyazakiKei KatohKoudoh Yamauchi
    • G11C17/00
    • G11C16/28G11C17/12H01L27/105H01L27/1052H01L27/115
    • A semiconductor integrated circuit has nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.
    • 半导体集成电路具有非易失性存储器和使用存储在非易失性存储器中的信息进行逻辑运算的逻辑电路。 非易失性存储器包括位线,字线和存储单元。 存储单元包括其栅电极与字线连接的MOS晶体管。 信息存储是根据MOS晶体管的一个源/漏电极是与源极线连接还是浮置而进行的。 在访问存储单元的操作中的预定时段之外的其他周期期间,构成存储单元的MOS晶体管的源/漏电极之间的电位差为零。 防止亚阈值泄漏电流在待机状态下通过存储单元。 在访问操作的预定周期期间,在MOS晶体管的源/漏电极之间产生电位差。 因此,位线电位可以通过字线选择来改变。