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1. 发明授权

US07116571B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07116571B2
公开(公告)日：2006-10-03
申请号：US10505216
申请日：2002-02-20
申请人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
发明人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
IPC分类号： G11C17/00
CPC分类号： G11C16/28 , G11C17/12 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A semiconductor integrated circuit has nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.
摘要翻译：半导体集成电路具有非易失性存储器和使用存储在非易失性存储器中的信息进行逻辑运算的逻辑电路。非易失性存储器包括位线，字线和存储单元。存储单元包括其栅电极与字线连接的MOS晶体管。信息存储是根据MOS晶体管的一个源/漏电极是与源极线连接还是浮置而进行的。在访问存储单元的操作中的预定时段之外的其他周期期间，构成存储单元的MOS晶体管的源/漏电极之间的电位差为零。防止亚阈值泄漏电流在待机状态下通过存储单元。在访问操作的预定周期期间，在MOS晶体管的源/漏电极之间产生电位差。因此，位线电位可以通过字线选择来改变。

2. 发明申请

US20070086229A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20070086229A1
公开(公告)日：2007-04-19
申请号：US11541605
申请日：2006-10-03
申请人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
发明人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
IPC分类号： G11C17/00
CPC分类号： G11C16/28 , G11C17/12 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line
摘要翻译：半导体集成电路具有使用非易失性存储器中存储的信息进行逻辑运算的非易失性存储器和逻辑电路。非易失性存储器包括位线，字线和存储单元。存储单元包括其栅电极与字线连接的MOS晶体管。信息存储是根据MOS晶体管的一个源/漏电极是与源极线连接还是浮置而进行的。在访问存储单元的操作中的预定时段之外的其他周期期间，构成存储单元的MOS晶体管的源/漏电极之间的电位差为零。防止亚阈值泄漏电流在待机状态下通过存储单元。在访问操作的预定周期期间，在MOS晶体管的源/漏电极之间产生电位差。因此，位线电位可以通过字线变化

3. 发明授权

US07324397B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07324397B2
公开(公告)日：2008-01-29
申请号：US11541605
申请日：2006-10-03
申请人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
发明人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C17/12 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line
摘要翻译：半导体集成电路具有使用非易失性存储器中存储的信息进行逻辑运算的非易失性存储器和逻辑电路。非易失性存储器包括位线，字线和存储单元。存储单元包括其栅电极与字线连接的MOS晶体管。信息存储是根据MOS晶体管的一个源/漏电极是与源极线连接还是浮置而进行的。在访问存储单元的操作中的预定时段之外的其他周期期间，构成存储单元的MOS晶体管的源/漏电极之间的电位差为零。防止亚阈值泄漏电流在待机状态下通过存储单元。在访问操作的预定周期期间，在MOS晶体管的源/漏电极之间产生电位差。因此，位线电位可以通过字线变化

4. 发明申请

US20050082572A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20050082572A1
公开(公告)日：2005-04-21
申请号：US10505216
申请日：2002-02-20
申请人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
发明人： Shinya Miyazaki , Kei Katoh , Koudoh Yamauchi
IPC分类号： G11C16/06 , G11C17/12 , G11C17/14 , H01L27/10 , H01L27/115
CPC分类号： G11C16/28 , G11C17/12 , H01L27/105 , H01L27/1052 , H01L27/115
摘要： A semiconductor integrated circuit has a nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.
摘要翻译：半导体集成电路具有使用非易失性存储器中存储的信息进行逻辑运算的非易失性存储器和逻辑电路。非易失性存储器包括位线，字线和存储单元。存储单元包括其栅电极与字线连接的MOS晶体管。信息存储是根据MOS晶体管的一个源/漏电极是与源极线连接还是浮置而进行的。在访问存储单元的操作中的预定时段之外的其他周期期间，构成存储单元的MOS晶体管的源/漏电极之间的电位差为零。防止亚阈值泄漏电流在待机状态下通过存储单元。在访问操作的预定周期期间，在MOS晶体管的源/漏电极之间产生电位差。因此，位线电位可以通过字线选择来改变。

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