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21. 发明授权

US08263465B2 Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 有权
标题翻译：使用耦合层的包括自对准金属纳米点的浮栅形成存储器的方法
公开(公告)号：US08263465B2
公开(公告)日：2012-09-11
申请号：US12754408
申请日：2010-04-05
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/339
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

22. 发明授权

US07723186B2 Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 有权
标题翻译：使用耦合层的包括自对准金属纳米点的浮栅形成存储器的方法
公开(公告)号：US07723186B2
公开(公告)日：2010-05-25
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336 , H01L21/30
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

23. 发明授权

US07582529B2 Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation 有权
标题翻译：使用集成外围电路和预隔离存储器单元形成制造非易失性存储器的方法
公开(公告)号：US07582529B2
公开(公告)日：2009-09-01
申请号：US12061641
申请日：2008-04-02
申请人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
发明人： George Matamis , Takashi Orimoto , Masaaki Higashitani , James Kai , Tuan Pham
IPC分类号： H01L21/8247
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。形成条带限定了所得电荷存储结构在列方向上的尺寸。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。

24. 发明申请

US20090189211A1 Non-Volatile Memory Arrays Having Dual Control Gate Cell Structures And A Thick Control Gate Dielectric And Methods Of Forming 有权
标题翻译：具有双重控制栅极单元结构和厚控制栅介质的非易失性存储器阵列和形成方法
公开(公告)号：US20090189211A1
公开(公告)日：2009-07-30
申请号：US12020428
申请日：2008-01-25
申请人： Takashi Orimoto , George Matamis , James Kai
发明人： Takashi Orimoto , George Matamis , James Kai
IPC分类号： H01L29/788 , H01L21/3205
CPC分类号： H01L27/11521 , H01L27/11519
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.
摘要翻译：提供了具有双控制栅极存储单元的非易失性半导体存储器件和形成方法。电荷存储层被蚀刻成沿着行方向延伸穿过衬底表面的条带，其间具有隧道介电层。所得到的条带可以在行方向上是连续的，或者可以包括单独的电荷存储区域，如果沿着它们的行方向上的长度被划分。第二层电介质材料沿着条的侧壁和隧道介电层之间的空间形成。第二层被蚀刻到条带之间的空间中覆盖隧道介电层的区域中。沿着条的侧壁的暴露部分和在它们之间的空间中的第二介电层上方形成中间介电层。控制栅极材料层沉积在条带之间的空间中。所得到的控制栅极通过中间介电层和通过隧道介电层，第二介电材料层和中间介质层从衬底表面与条分离。

25. 发明申请

US20080318381A1 METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE 有权
标题翻译：使用回放间隔技术形成高密度半导体器件的方法
公开(公告)号：US20080318381A1
公开(公告)日：2008-12-25
申请号：US11765866
申请日：2007-06-20
申请人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
发明人： George Matamis , James Kai , Takashi Orimoto , Nima Mokhlesi
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.
摘要翻译：公开了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。可以处理第一组间隔件以提供平面和平行的侧壁。可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

26. 发明授权

US07939407B2 Composite charge storage structure formation in non-volatile memory using etch stop technologies 有权
标题翻译：使用蚀刻停止技术在非易失性存储器中形成复合电荷存储结构
公开(公告)号：US07939407B2
公开(公告)日：2011-05-10
申请号：US12615154
申请日：2009-11-09
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译：包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。可以增加各个存储单元尺寸的一致性。

27. 发明授权

US07592223B2 Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation 有权
标题翻译：使用集成选择和外围电路和后隔离存储器单元形成制造非易失性存储器的方法
公开(公告)号：US07592223B2
公开(公告)日：2009-09-22
申请号：US12061642
申请日：2008-04-02
申请人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
发明人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
IPC分类号： H01L21/8247
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。光刻胶也被应用在外围电路区域。在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

28. 发明申请

US20090163008A1 Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的光刻空间定义电荷存储区域
公开(公告)号：US20090163008A1
公开(公告)日：2009-06-25
申请号：US11960513
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/28
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译：在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域的第一电荷存储区域。

29. 发明申请

US20090162951A1 Enhanced Endpoint Detection In Non-Volatile Memory Fabrication Processes 有权
标题翻译：在非易失性存储器制造过程中增强端点检测
公开(公告)号：US20090162951A1
公开(公告)日：2009-06-25
申请号：US11960485
申请日：2007-12-19
申请人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
发明人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译：提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。从端点区域去除第一电荷存储层以暴露隧道电介质区域。第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。

30. 发明申请

US20080268596A1 Methods Of Fabricating Non-Volatile Memory With Integrated Select And Peripheral Circuitry And Post-Isolation Memory Cell Formation 有权
标题翻译：使用集成选择和外围电路和后隔离存储器单元形成的非易失性存储器的制造方法
公开(公告)号：US20080268596A1
公开(公告)日：2008-10-30
申请号：US12061642
申请日：2008-04-02
申请人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
发明人： Tuan Pham , Takashi Orimoto , Masaaki Higashitani , James Kai , George Matamis
IPC分类号： H01L21/336
CPC分类号： H01L27/11543 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11541
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.
摘要翻译：提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。光刻胶也被应用在外围电路区域。在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

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