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21. 发明授权

US07341943B2 Post etch copper cleaning using dry plasma 有权
标题翻译：使用干等离子体进行铜蚀刻铜蚀刻
公开(公告)号：US07341943B2
公开(公告)日：2008-03-11
申请号：US11053018
申请日：2005-02-08
申请人： Chen-Nan Yeh , Miao-Ju Hsu , Hun-Jan Tao
发明人： Chen-Nan Yeh , Miao-Ju Hsu , Hun-Jan Tao
IPC分类号： H01L21/44
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/321 , H01L21/76802
摘要： A method for post-etch copper cleaning uses a hydrogen plasma with a trace gas additive constituting about 3-10 percent of the plasma by volume to clean a copper surface exposed by etching. The trace gas may be atomic nitrogen or other species having an atomic mass of 15 or greater. The trace gas adds a sputtering aspect to the plasma cleaning and removes polymeric etch by-products and polymeric and other residuals formed during the deposition of dielectric materials or etch stop layers over the copper surface. An anti-corrosion solvent may be used to passivate the copper surface prior to formation of the dielectric materials or etch stop layers.
摘要翻译：用于蚀刻后铜清洗的方法使用构成等离子体体积的约3-10％的痕量气体添加剂的氢等离子体来清洁通过蚀刻暴露的铜表面。痕量气体可以是原子态氮或其原子质量为15以上的物质。痕量气体在等离子体清洗中增加了溅射方面，并且去除了在铜表面沉积介电材料或蚀刻停止层期间形成的聚合物蚀刻副产物和聚合物和其它残余物。在形成介电材料或蚀刻停止层之前，可以使用防腐溶剂来钝化铜表面。

22. 发明授权

US07307009B2 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US07307009B2
公开(公告)日：2007-12-11
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

23. 发明申请

US20070184669A1 Via structures and trench structures and dual damascene structures 有权
标题翻译：通过结构和沟槽结构和双镶嵌结构
公开(公告)号：US20070184669A1
公开(公告)日：2007-08-09
申请号：US11732883
申请日：2007-04-04
申请人： Yi-Chen Huang , Chien Fu , Ming-Hong Hsieh , Hui Ouyang , Yi-Nien Su , Hun-Jan Tao
发明人： Yi-Chen Huang , Chien Fu , Ming-Hong Hsieh , Hui Ouyang , Yi-Nien Su , Hun-Jan Tao
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76865 , H01L21/76808 , H01L21/76843 , H01L21/76846 , H01L21/76862
摘要： Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.
摘要翻译：公开了通孔和沟槽结构和制造方法。该结构包括电介质层中的导电层，以及介电层中与导电层表面的一部分接触的通孔结构。通孔结构包括与第一导电层的表面的部分接触的导电衬垫。在电介质中的通孔结构上形成沟槽结构，而沟槽中没有导电衬垫层。

24. 发明申请

US20070128736A1 Multi-metal-oxide high-k gate dielectrics 有权
标题翻译：多金属氧化物高k栅极电介质
公开(公告)号：US20070128736A1
公开(公告)日：2007-06-07
申请号：US11328933
申请日：2006-01-10
申请人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
发明人： Vincent Chang , Fong-Yu Yen , Peng-Soon Lim , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/02175 , H01L21/0228 , H01L21/02337 , H01L21/28079 , H01L21/28194 , H01L21/3141 , H01L21/31645 , H01L29/1054 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/6659 , H01L29/7833
摘要： A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.
摘要翻译：提供具有高k电介质的半导体结构及其制造方法。一种方法包括在衬底上形成第一介电层，在第一介电层上形成金属层，在金属层上方形成第二电介质层。一种方法还包括在氧化环境中退火衬底，直到三层形成均匀的高k电介质层。形成第一和第二电介质层包括诸如原子层沉积（ALD）或化学气相沉积（CVD）的非等离子体沉积工艺。具有高k电介质的半导体器件包括非晶高k电介质层，其中非晶高k电介质层包括第一氧化金属和第二氧化金属。所有氧化金属的原子比在非晶高k电介质层内基本均匀。

25. 发明授权

US07208331B2 Methods and structures for critical dimension and profile measurement 有权
标题翻译：关键尺寸和型材测量的方法和结构
公开(公告)号：US07208331B2
公开(公告)日：2007-04-24
申请号：US10949037
申请日：2004-09-24
申请人： Jyu-Horng Shieh , Wen-Chih Chiou , Peng-Fu Hsu , Baw-Ching Perng , Hun-Jan Tao , Chia-Jen Chen
发明人： Jyu-Horng Shieh , Wen-Chih Chiou , Peng-Fu Hsu , Baw-Ching Perng , Hun-Jan Tao , Chia-Jen Chen
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34
摘要： Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.
摘要翻译：公开了关键尺寸或轮廓测量的方法和结构。该方法提供其中具有周期性开口的基板。在开口中形成材料层，基本上平坦化基底的表面。将散射方法应用于具有临界尺寸（CD）或轮廓测量的材料层的基底。

26. 发明申请

US20070026668A1 LOW K DIELECTRIC SURFACE DAMAGE CONTROL 有权
标题翻译：低K电介质表面损伤控制
公开(公告)号：US20070026668A1
公开(公告)日：2007-02-01
申请号：US11457888
申请日：2006-07-17
申请人： Hun-Jan Tao , Ryan Chen , Mong-Song Liang
发明人： Hun-Jan Tao , Ryan Chen , Mong-Song Liang
IPC分类号： H01L21/465
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76807
摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.
摘要翻译：公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

27. 发明申请

US20060205224A1 Large-scale trimming for ultra-narrow gates 审中-公开
公开(公告)号：US20060205224A1
公开(公告)日：2006-09-14
申请号：US11318934
申请日：2005-12-27
申请人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
发明人： Ming-Jie Huang , Shu-Chih Yang , Huan-Just Lin , Yung-Tin Chen , Hun-Jan Tao
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/28123
摘要： Large-scale trimming for forming ultra-narrow gates for semiconductor devices is disclosed. A hard mask layer on a semiconductor wafer below a patterned soft mask layer on the semiconductor wafer is etched to narrow a width of the hard mask layer. The hard mask layer is trimmed to further narrow the width of the hard mask layer, where the soft mask layer has been removed. At least a gate electrode layer below the hard mask layer on the semiconductor wafer is etched, resulting in the gate electrode layer having a width substantially identical to the width of the hard mask layer as trimmed. The gate electrode layer as etched forms the ultra-narrow gate electrode on the semiconductor wafer, where the hard mask layer has been removed.

28. 发明授权

US07078351B2 Photoresist intensive patterning and processing 失效
标题翻译：光刻胶强化图案和加工
公开(公告)号：US07078351B2
公开(公告)日：2006-07-18
申请号：US10361875
申请日：2003-02-10
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/30604 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/76802
摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.
摘要翻译：首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

29. 发明授权

US07074727B2 Process for improving dielectric properties in low-k organosilicate dielectric material 失效
标题翻译：改进低k有机硅酸盐介电材料介电性能的方法
公开(公告)号：US07074727B2
公开(公告)日：2006-07-11
申请号：US10615628
申请日：2003-07-09
申请人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： C08G77/00 , H01L21/768
CPC分类号： C08G77/38
摘要： Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.
摘要翻译：低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。

30. 发明申请

US20060086690A1 Dielectric etching method to prevent photoresist damage and bird's beak 审中-公开
标题翻译：电介质蚀刻法防止光刻胶损伤和鸟嘴
公开(公告)号：US20060086690A1
公开(公告)日：2006-04-27
申请号：US10971265
申请日：2004-10-21
申请人： Ming-Huan Tsai , Fong-Yuh Yen , Hun-Jan Tao
发明人： Ming-Huan Tsai , Fong-Yuh Yen , Hun-Jan Tao
IPC分类号： C23F1/00 , C03C25/68 , B44C1/22
CPC分类号： H01L21/31116
摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.
摘要翻译：提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。

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