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21. 发明申请

US20100259963A1 Data line layouts 有权
标题翻译：数据线布局
公开(公告)号：US20100259963A1
公开(公告)日：2010-10-14
申请号：US12659883
申请日：2010-03-24
申请人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Hyang-Ja Yang , Choong-Sun Shin , Hak-Soo Yu , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C11/4097
摘要： A data line layout includes column selection lines arranged in a first direction at a layer on a memory cell array region, and data lines arranged in the first direction at the layer, the data lines being connected between I/O sense amplifiers and I/O pads.
摘要翻译：数据线布局包括在存储单元阵列区域上的层上沿着第一方向布置的列选择线以及沿着该层的第一方向布置的数据线，数据线连接在I / O读出放大器和I / O之间垫

22. 发明授权

US07489570B2 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US07489570B2
公开(公告)日：2009-02-10
申请号：US11480447
申请日：2006-07-05
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

23. 发明授权

US6128233A Data transmission circuitry of a synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件的数据传输电路
公开(公告)号：US6128233A
公开(公告)日：2000-10-03
申请号：US370842
申请日：1999-08-09
申请人： Hak-Soo Yu , Su-Chul Kim
发明人： Hak-Soo Yu , Su-Chul Kim
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C11/417 , G11C7/00
CPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096 , G11C7/1006 , G11C7/1072 , G11C7/22
摘要： A synchronous memory comprising: a memory cell array being comprised of a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals; a first register circuit for storing a plurality of input data bits in response to the internal clock signal and the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array; an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.
摘要翻译：一种同步存储器，包括：由多个存储单元组成的存储单元阵列; 时钟控制电路，用于接收第一时钟信号，第二时钟信号和第三时钟信号，并用于产生内部时钟信号，多个控制信号和多个标志信号; 第一寄存器电路，用于响应于内部时钟信号和控制信号而存储多个输入数据位; 第二寄存器电路，用于响应于内部时钟信号和控制信号而存储标志信号; 写入驱动电路，用于在写入周期期间响应于标志信号，将通过第一寄存器电路的输入数据位写入存储单元阵列; 耦合到存储单元阵列的读出放大器电路; 地址比较器电路，用于接收读和写地址信号，并用于产生第一，第二和第三组合信号; 以及用于将通过第一寄存器电路的输入数据位和通过第二寄存器电路的标志信号传送到器件的输出端的开关电路。

24. 发明授权

US08830715B2 Semiconductor memory device including vertical channel transistors 有权
标题翻译：半导体存储器件包括垂直沟道晶体管
公开(公告)号：US08830715B2
公开(公告)日：2014-09-09
申请号：US13304851
申请日：2011-11-28
申请人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
发明人： Hak-Soo Yu , Su-A Kim , Hong-Sun Hwang , Chul-Woo Park
IPC分类号： G11C5/02 , G11C11/34 , H01L27/108 , G11C7/02 , G11C7/06
CPC分类号： G11C7/02 , G11C7/062 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897
摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.
摘要翻译：公开了一种半导体存储器件。半导体存储器件包括存储器阵列块，第一字线和第二字线。存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元晶体管。第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管。

25. 发明授权

US07697314B2 Data line layout and line driving method in semiconductor memory device 有权
标题翻译：半导体存储器件中的数据线布局和线驱动方法
公开(公告)号：US07697314B2
公开(公告)日：2010-04-13
申请号：US12006502
申请日：2008-01-03
申请人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/1051 , G11C7/1069 , G11C7/18 , G11C11/417
摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.
摘要翻译：数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

26. 发明授权

US07656723B2 Semiconductor memory device with hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体存储器件
公开(公告)号：US07656723B2
公开(公告)日：2010-02-02
申请号：US12347239
申请日：2008-12-31
申请人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
发明人： Nam-Seog Kim , Jong-Cheol Lee , Hak-Soo Yu , Uk-Rae Cho
IPC分类号： G11C7/22
CPC分类号： G11C11/417 , G11C7/18 , G11C8/12
摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.
摘要翻译：半导体存储器件具有分层位线结构。半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

27. 发明授权

US06091663A Synchronous burst semiconductor memory device with parallel input/output data strobe clocks 有权
标题翻译：具有并行输入/输出数据选通时钟的同步脉冲串半导体存储器件
公开(公告)号：US06091663A
公开(公告)日：2000-07-18
申请号：US137645
申请日：1998-08-20
申请人： Su-Chul Kim , Hak-Soo Yu , Min-Chul Chung
发明人： Su-Chul Kim , Hak-Soo Yu , Min-Chul Chung
IPC分类号： G11C11/407 , G06F12/00 , G11C7/10 , G11C11/409 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1051
摘要： A synchronous burst semiconductor memory device operating in synchronism with at least one external clock signal and capable of accessing data on every edge of the external clock signal is provided. The burst memory device includes a clock generator for generating a number of data output/input strobe clock signals synchronized with the external clock signal in response to a plurality of input information signals, and a data-out/in buffer for outputting/inputting internal/external data in synchronism with the data output/input strobe clock signals.
摘要翻译：提供了与至少一个外部时钟信号同步操作且能够访问外部时钟信号的每个边缘上的数据的同步突发半导体存储器件。突发存储器件包括：时钟发生器，用于响应于多个输入信息信号产生与外部时钟信号同步的多个数据输出/输入选通时钟信号;以及数据输出/输入缓冲器，用于输出/输入内部/ 外部数据与数据输出/输入选通时钟信号同步。

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