专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08156459B1 Detecting differences between high level block diagram models 有权
标题翻译：检测高级框图模型之间的差异
公开(公告)号：US08156459B1
公开(公告)日：2012-04-10
申请号：US12615415
申请日：2009-11-10
申请人： Jingzhao Ou , Chi Bun Chan
发明人： Jingzhao Ou , Chi Bun Chan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F8/10
摘要： A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and cannot compare differences between models created with third party design environments. The present invention increases interoperability and capabilities of existing circuit design environments, and achieves an advance in the art, by converting high level block diagram models to a user readable text-based format and performing a text-based differential analysis on the converted models to determine differences.
摘要翻译：使用基于文本分析的高级框图模型之间的差异检测方法。以前确定高级框图模型之间的差异的方法通过遍历块层次结构导出差异，这是复杂的，并且无法比较使用第三方设计环境创建的模型之间的差异。本发明提高了现有电路设计环境的互操作性和能力，并且通过将高级框图模型转换为用户可读的基于文本的格式并对转换的模型执行基于文本的差分分析来实现本领域的进步，以确定差异

22. 发明授权

US08020127B1 Clock frequency exploration for circuit designs having multiple clock domains 有权
标题翻译：具有多个时钟域的电路设计的时钟频率探测
公开(公告)号：US08020127B1
公开(公告)日：2011-09-13
申请号：US12275658
申请日：2008-11-21
申请人： Chi Bun Chan , Jingzhao Ou , Jeffrey D. Stroomer
发明人： Chi Bun Chan , Jingzhao Ou , Jeffrey D. Stroomer
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045
摘要： A computer-implemented method of circuit design can include receiving clock frequency constraints defining relationships between clock frequencies of a plurality of clock domains of a circuit design specified within a high-level modeling system (305) and receiving a cost function that is dependent upon the clock frequencies of the plurality of clock domains (310). A feasibility result can be determined according to the clock frequency constraints and the cost function (315). The feasibility result can indicate whether a clock frequency assignment exists that specifies a clock frequency for each of the plurality of clock domains that does not violate any clock frequency constraint. The feasibility result can be output (315).
摘要翻译：计算机实现的电路设计方法可以包括接收定义在高级建模系统（305）内指定的电路设计的多个时钟域的时钟频率之间的关系的时钟频率约束，并且接收依赖于多个时钟域（310）的时钟频率。可以根据时钟频率约束和成本函数确定可行性结果（315）。可行性结果可以指示是否存在指定不违反任何时钟频率约束的多个时钟域中的每一个的时钟频率的时钟频率分配。可以输出可行性结果（315）。

23. 发明授权

US07852109B1 Method and apparatus for supplying a clock to a device under test 有权
标题翻译：向被测设备提供时钟的方法和装置
公开(公告)号：US07852109B1
公开(公告)日：2010-12-14
申请号：US12335466
申请日：2008-12-15
申请人： Chi Bun Chan , Jingzhao Ou
发明人： Chi Bun Chan , Jingzhao Ou
IPC分类号： H03K19/00
CPC分类号： H03K19/17764 , G01R31/31724 , G01R31/318516
摘要： A method and apparatus involves operating a circuit having a test circuit interrupt input terminal (INTERRUPT), having a test circuit clock output terminal (DUT_CLK), and having first and second operational modes. In the first operational mode the circuit supplies a test circuit clock signal to the test circuit clock output terminal. The circuit responds to receipt of an occurrence of a test circuit interrupt at the test circuit interrupt input terminal by then operating in the second operational mode. In the second operational mode the circuit refrains from supplying the test circuit clock signal to the test circuit clock output terminal.
摘要翻译：一种方法和装置包括操作具有测试电路中断输入端（INTERRUPT）的电路，具有测试电路时钟输出端（DUT_CLK），并具有第一和第二操作模式。在第一操作模式下，电路向测试电路时钟输出端提供测试电路时钟信号。该电路在测试电路中断输入端接收到测试电路中断的发生，然后在第二操作模式下运行。在第二操作模式中，电路不会将测试电路时钟信号提供给测试电路时钟输出端。

24. 发明授权

US08600722B1 Method and apparatus for providing program-based hardware co-simulation of a circuit design 有权
标题翻译：用于提供电路设计的基于程序的硬件协同仿真的方法和装置
公开(公告)号：US08600722B1
公开(公告)日：2013-12-03
申请号：US11805133
申请日：2007-05-22
申请人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
发明人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.
摘要翻译：描述了一种用于提供电路设计的基于程序的硬件协同仿真的方法和装置。在一个示例中，实现用于可编程逻辑以建立被测设计（DUT）的电路设计。使用由应用程序编程接口（API）定义的原语以编程方式生成协同仿真模型。通过使用DUT配置可编程逻辑来模拟电路设计，并通过执行协同仿真模型驱动协同仿真引擎与DUT进行通信。

25. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

26. 发明授权

US07636653B1 Point-to-point ethernet hardware co-simulation interface 有权
标题翻译：点到点以太网硬件协同仿真界面
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译：与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。

27. 发明授权

US08868396B1 Verification and debugging using heterogeneous simulation models 有权
标题翻译：使用异构仿真模型进行验证和调试
公开(公告)号：US08868396B1
公开(公告)日：2014-10-21
申请号：US12605077
申请日：2009-10-23
申请人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
发明人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
摘要翻译：本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分设计负责的差异。

28. 发明授权

US08102188B1 Method of and system for implementing a circuit in a device having programmable logic 有权
标题翻译：用于在具有可编程逻辑的设备中实现电路的方法和系统
公开(公告)号：US08102188B1
公开(公告)日：2012-01-24
申请号：US12757770
申请日：2010-04-09
申请人： Chi Bun Chan , Nabeel Shirazi
发明人： Chi Bun Chan , Nabeel Shirazi
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.
摘要翻译：公开了一种在具有可编程资源和预定量的可用内部存储器的设备中实现电路的方法。该方法包括利用电路设计来配置设备的可编程资源; 将第一页数据存储在随机存取存储器块中; 当实现电路设计时，确定页面错误同时与随机存取存储器块接口; 执行所述设备的部分重新配置，其中第二数据页被存储在所述随机存取存储器块中; 并访问第二页数据。还公开了一种在具有可编程逻辑的设备中实现电路的系统。

29. 发明授权

US08812289B1 Simulation that transfers port values of a design block via a configuration block of a programmable device 有权
标题翻译：模拟通过可编程设备的配置块传输设计块的端口值
公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译：模拟电子系统的方法。在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列并且生成用于传送第一和第二序列值的访问事务。软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。响应于访问事务，控制块还控制设计块的仿真。

30. 发明授权

US08650019B1 Linking untimed data-path and timed control-path models 有权
标题翻译：链接未定义的数据路径和定时控制路径模型
公开(公告)号：US08650019B1
公开(公告)日：2014-02-11
申请号：US12695800
申请日：2010-01-28
申请人： Arvind Sundararajan , Chi Bun Chan
发明人： Arvind Sundararajan , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Approaches for creating a timed hybrid simulation model for a circuit design specification. An untimed, high-level language (HLL) data-path model is input, along with an HLL data-path interface specification that specifies input ports of the HLL data-path model. A hardware description language (HDL) control-path model that specifies port attributes and associated stitching directives is generated. Each stitching directive specifies a control port and an associated one of the input ports of the HLL data-path model. The HLL data-path and HDL control-path models are linked (314) to create the timed hybrid simulation model, and the timed hybrid simulation model is stored in a processor-readable storage medium.
摘要翻译：为电路设计规范创建定时混合仿真模型的方法。输入未定义的高级语言（HLL）数据路径模型，以及指定HLL数据路径模型的输入端口的HLL数据路径接口规范。生成指定端口属性和关联拼接指令的硬件描述语言（HDL）控制路径模型。每个拼接指令指定HLL数据路径模型的控制端口和关联的一个输入端口。将HLL数据路径和HDL控制路径模型链接（314）以创建定时混合仿真模型，并将定时混合仿真模型存储在处理器可读存储介质中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式