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21. 发明申请

US20060009043A1 Methods of forming a composite dielectric structure and methods of manufacturing a semiconductor device including a composite dielectric structure 有权
公开(公告)号：US20060009043A1
公开(公告)日：2006-01-12
申请号：US11176715
申请日：2005-07-07
申请人： Hag-Ju Cho , Yu-Gyun Shin
发明人： Hag-Ju Cho , Yu-Gyun Shin
IPC分类号： H01L21/469
CPC分类号： H01L21/0214 , H01L21/02126 , H01L21/02142 , H01L21/02164 , H01L21/02172 , H01L21/022 , H01L21/02332 , H01L21/0234 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L27/10814 , H01L27/10852 , H01L27/10873 , H01L27/11502 , H01L27/11507 , H01L28/91 , H01L29/513 , H01L29/517
摘要： Some methods that are provided form a composite dielectric structure on a substrate. A first dielectric layer that includes metal and oxygen is formed on a substrate. A preliminary dielectric layer that includes silicon is formed on the first dielectric layer. A plasma nitriding treatment is performed on the preliminary dielectric layer to change it into a second dielectric layer. The composite dielectric structure includes the second dielectric layer and the first dielectric layer. Other methods form a semiconductor device that includes the composite dielectric structure.

22. 发明授权

US08557651B2 Method of manufacturing a semiconductor device using an etchant 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US08557651B2
公开(公告)日：2013-10-15
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/8238
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

23. 发明申请

US20110217833A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING AN ETCHANT 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US20110217833A1
公开(公告)日：2011-09-08
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

24. 发明申请

US20080164581A1 ELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：电子设备及其制造方法
公开(公告)号：US20080164581A1
公开(公告)日：2008-07-10
申请号：US11969679
申请日：2008-01-04
申请人： Hag-Ju Cho , Tom Schram , Stefan De Gendt
发明人： Hag-Ju Cho , Tom Schram , Stefan De Gendt
IPC分类号： H01L21/283 , H01L23/58
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28194 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： An electronic device and a process for manufacturing the same are disclosed. In one aspect, the device comprises an electrode comprising a metal compound selected from the group of tantalum carbide, tantalum carbonitride, hafnium carbide and hafnium carbonitride. The device further comprises a high-k dielectric layer of a hafnium oxide comprising nitrogen and silicon, the high-k dielectric layer having a k value of at least 4.0. The device further comprises a nitrogen and/or silicon and/or carbon barrier layer placed between the electrode and the high-k dielectric layer. The nitrogen and/or silicon and/or carbon barrier layer comprises one or more metal oxides, the metal of the metal oxides being selected from the group of lanthanides, aluminium or hafnium.
摘要翻译：公开了一种电子设备及其制造方法。一方面，该装置包括一种包含选自碳化钽，碳氮化钽，碳化铪和碳氮化铪的金属化合物的电极。该器件还包括包含氮和硅的氧化铪的高k电介质层，所述高k电介质层的k值至少为4.0。该装置还包括置于电极和高k电介质层之间的氮和/或硅和/或碳阻挡层。氮和/或硅和/或碳阻挡层包含一种或多种金属氧化物，金属氧化物的金属选自镧系元素，铝或铪。

25. 发明授权

US08313993B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08313993B2
公开(公告)日：2012-11-20
申请号：US12358188
申请日：2009-01-22
申请人： Hag-Ju Cho , Anabela Veloso , HongYu Yu , Stefan Kubicek , Shou-Zen Chang
发明人： Hag-Ju Cho , Anabela Veloso , HongYu Yu , Stefan Kubicek , Shou-Zen Chang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462 , H01L27/088 , H01L27/092 , H01L29/513
摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
摘要翻译：公开了一种双功能半导体器件及其制造方法。一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。选择金属层以确定第一功函数。选择第一介电覆盖层以确定第二功函数。

26. 发明申请

US20120238067A1 Methods of Fabricating Semiconductor Devices Having Gate Trenches 审中-公开
标题翻译：制造具有栅极沟槽的半导体器件的方法
公开(公告)号：US20120238067A1
公开(公告)日：2012-09-20
申请号：US13422223
申请日：2012-03-16
申请人： Won-Cheol Jeong , Yun-Young Yeoh , Dong-Won Kim , Hong-Bae Park , Hag-Ju Cho
发明人： Won-Cheol Jeong , Yun-Young Yeoh , Dong-Won Kim , Hong-Bae Park , Hag-Ju Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/4966 , H01L29/517 , H01L29/78
摘要： Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.
摘要翻译：制造半导体器件的方法包括提供其中限定有沟道区的衬底; 在所述基板上形成绝缘层; 形成用于形成具有侧壁部分，底部和所述侧壁部分与所述绝缘层上的所述底部之间的边缘部分的栅电极的栅极沟槽，所述栅电极沟槽与所述沟道区重叠; 以及在所述栅电极沟槽中形成栅电极。形成栅电极包括在栅电极沟槽中形成第一金属层图案，并在第一金属层图案上形成第二金属层图案。

27. 发明授权

US08119511B2 Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same 有权
标题翻译：具有提高抗擦除饱和度的非易失性存储器件及其制造方法
公开(公告)号：US08119511B2
公开(公告)日：2012-02-21
申请号：US13080562
申请日：2011-04-05
申请人： Bogdan Govoreanu , HongYu Yu , Hag-Ju Cho
发明人： Bogdan Govoreanu , HongYu Yu , Hag-Ju Cho
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
摘要翻译：一种非易失性存储器件，其具有位于第二电介质（互补或阻塞电介质）顶部的控制栅极，至少与第二电介质接触的控制栅极的底层被构造成具有预定义的高功函数的材料并且在完全器件制造之后显示出与一组高k材料接触时降低其功能的趋势。至少第二电介质的顶层将控制栅极的底层与第二电介质的其余部分分开，以预定的高k材料构成，选择在组外部，以避免工作功能的降低控制门底层的材料。在制造方法中，在施加控制栅极之前，在第二电介质中产生顶层。

28. 发明申请

US20110183509A1 Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same 有权
标题翻译：具有改善的消除饱和度的抗扰性的非易失性存储器件及其制造方法相同
公开(公告)号：US20110183509A1
公开(公告)日：2011-07-28
申请号：US13080562
申请日：2011-04-05
申请人： Bogdan Govoreanu , HongYu Yu , Hag-Ju Cho
发明人： Bogdan Govoreanu , HongYu Yu , Hag-Ju Cho
IPC分类号： H01L21/28
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/7881
摘要： A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.
摘要翻译：一种非易失性存储器件，其具有位于第二电介质（互补或阻塞电介质）顶部的控制栅极，至少与第二电介质接触的控制栅极的底层被构造成具有预定义的高功函数的材料并且在完全器件制造之后显示出与一组高k材料接触时降低其功能的趋势。至少第二电介质的顶层将控制栅极的底层与第二电介质的其余部分分开，以预定的高k材料构成，选择在组外部，以避免工作功能的降低控制门底层的材料。在制造方法中，在施加控制栅极之前，在第二电介质中产生顶层。

29. 发明申请

US20090184376A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090184376A1
公开(公告)日：2009-07-23
申请号：US12358188
申请日：2009-01-22
申请人： Hag-Ju Cho , Anabela Veloso , HongYu Yu , Stefan Kubicek , Shou-Zen Chang
发明人： Hag-Ju Cho , Anabela Veloso , HongYu Yu , Stefan Kubicek , Shou-Zen Chang
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823857 , H01L21/823462 , H01L27/088 , H01L27/092 , H01L29/513
摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
摘要翻译：公开了一种双功能半导体器件及其制造方法。一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。选择金属层以确定第一功函数。选择第一介电覆盖层以确定第二功函数。

30. 发明授权

US6001660A Methods of forming integrated circuit capacitors using metal reflow techniques 失效
标题翻译：使用金属回流技术形成集成电路电容器的方法
公开(公告)号：US6001660A
公开(公告)日：1999-12-14
申请号：US969672
申请日：1997-11-13
申请人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
发明人： Young-soh Park , Sang-in Lee , Cheol-seong Hwang , Doo-sup Hwang , Hag-Ju Cho
IPC分类号： C23C14/14 , C23C14/58 , H01L21/02 , H01L21/28 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01G7/06
CPC分类号： H01L28/60 , H01L21/76882
摘要： Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.
摘要翻译：形成集成电路电容器的方法包括以下步骤：在半导体衬底的表面上形成电绝缘层，然后对电绝缘层进行构图以在其中限定接触孔。然后在接触孔的至少一部分中形成阻挡金属层。然后在阻挡金属层上形成下电极金属层，然后通过在氮气环境中在大于约650℃的温度下回流下电极金属层来平坦化，以限定较低的电容器电极。然后在下部电容器电极上形成具有高介电常数的材料层。然后在电介质层上形成上电容器电极，与下电容器电极相对。介电层可以包括Ba（Sr，Ti）O3，Pb（Zr，Ti）O3，Ta2O5，SiO2，SiN3，SrTiO3，PZT，SrBi2Ta2O9，（Pb，La）（Zr，Ti）O3和Bi4Ti3O12。根据本发明的一个实施例，图案化电绝缘层的步骤包括图案化电绝缘层以限定其中露出半导体衬底的表面的接触孔。形成阻挡金属层的步骤还优选包括在接触孔的侧壁上和基底的暴露面上沉积保形阻挡金属层。阻挡金属层可以选自TiN，CoSi，TaSiN，TiSiN，TaSi，TiSi，Ta和TaN。

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