专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06417526B2 Semiconductor device having a rectifying junction and method of manufacturing same 有权
标题翻译：具有整流结的半导体装置及其制造方法
公开(公告)号：US06417526B2
公开(公告)日：2002-07-09
申请号：US09288395
申请日：1999-04-08
申请人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
发明人： Adam R. Brown , Godefridus A. M. Hurkx , Michael S. Peter , Hendrik G. A. Huizing , Wiebe B. De Boer
IPC分类号： H01L29861
CPC分类号： H01L29/885 , H01L29/32 , Y10S438/979
摘要： The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.
摘要翻译：本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。两个区域（1,2）各自设置有连接导体（3,4）。这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快地切换。在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压器件仍然低于发生错配位错的水平。令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。没有错配位错具有额外的优点，即该装置非常可靠。如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。所述产品的安全上限为30nm％。

22. 发明授权

US06355971B2 Semiconductor switch devices having a region with three distinct zones and their manufacture 失效
标题翻译：具有具有三个不同区域的区域及其制造的半导体开关器件
公开(公告)号：US06355971B2
公开(公告)日：2002-03-12
申请号：US09257631
申请日：1999-02-25
申请人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
发明人： Holger Schligtenhorst , Godefridus A. M. Hurkx , Andrew M. Warwick
IPC分类号： H01L2970
CPC分类号： H01L29/66136 , H01L29/66295 , H01L29/7325 , H01L29/868
摘要： In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P−) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). The high-doped zone (25) which may form a contact zone has a doping concentration (P++) which is higher than that of the low-doped zone (23) and which decreases towards the low-doped zone (23). The distinct additional zone (24) has an additional doping concentration (P+) which is lower than the doping concentration (P++) of the high-doped zone (25) and which decreases towards the low-doped zone (23). This triple-zone formation for the first region (1) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P−) can be used for low-doped zone (23) so that, in the off-state of the device (T, D), this zone (23) and also the additional zone (24) can be fully depleted. The additional zone (24) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone (23) when the device (T, D) is being switched off.
摘要翻译：在诸如NPN晶体管（T）或功率开关二极管（D）的半导体开关器件中，一个导电类型的多区域第一区域（1）形成具有第二区域（2）的可切换pn结（12）的相反导电类型。根据本发明，该第一区域（1）包括三个不同的区域，即低掺杂区域（23），高掺杂区域（25）和中间附加区域（24）。低掺杂区域（23）由具有基本均匀的p型掺杂浓度（P-）的半导体本体部分（11）提供，并与第二区域（2）形成p-n结（12）。不同的附加区（24）存在于低掺杂区（23）和高掺杂区（25）之间。可形成接触区的高掺杂区（25）具有高于低掺杂区（23）的掺杂浓度（P ++），并且朝向低掺杂区（23）减小。不同的附加区域（24）具有低于高掺杂区域（25）的掺杂浓度（P ++）的附加掺杂浓度（P +），并且朝向低掺杂区域（23）减小。用于第一区域（1）的这种三区形成允许改变开关行为，例如，在设备（T，D）关闭期间的下降时间和能量耗散方面。对于低掺杂区域（23），可以使用非常低的掺杂（P-），使得在器件（T，D）的截止状态下，该区域（23）以及附加区域（24）可以充分耗尽具有其附加掺杂浓度的附加区域（24）提供了当器件（T，D）被切断时从低掺杂区域（23）提取残余电荷载流子的路径。

23. 发明授权

US5329481A Semiconductor device having a memory cell 失效
标题翻译：具有存储单元的半导体器件
公开(公告)号：US5329481A
公开(公告)日：1994-07-12
申请号：US989629
申请日：1992-12-14
申请人： Evert Seevinck , Maarten Vertregt , Godefridus A. M. Hurkx
发明人： Evert Seevinck , Maarten Vertregt , Godefridus A. M. Hurkx
IPC分类号： H01L21/8247 , G11C11/34 , H01L21/8229 , H01L27/102 , H01L27/115
CPC分类号： G11C11/34
摘要： A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).
摘要翻译：一种具有至少一个可编程存储单元的半导体器件，其包括具有第一导电类型的发射极（11）和集电极（12）的双极晶体管（T1）和具有第二导电类型的第二基极（10）。发射极（11）和集电极（12）分别耦合到第一电源线（100）和第二供电线（200）。基极（10）通过控制晶体管（T2）耦合到写入装置（WRITE）。读取装置（READ）包括在第一电源线（100）和第二电源线（200）之间延伸的电流路径（I）中，并且包括发射器（11）和集电极（12）之间的电流路径。在优选实施例中，收集器（12）还经由可切换负载（T5）耦合到第二供电管线（200）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式