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21. 发明授权

US08575697B2 SRAM-type memory cell 有权
标题翻译： SRAM型存储单元
公开(公告)号：US08575697B2
公开(公告)日：2013-11-05
申请号：US13039167
申请日：2011-03-02
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： H01L27/11 , H01L27/12 , G11C5/06 , G11C11/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/1203
摘要： An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.
摘要翻译：一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。第一和第二电位可以根据电池控制操作的类型进行调制。

22. 发明授权

US08432216B2 Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer 有权
标题翻译： SeOI衬底上的数据通道单元，在绝缘层下面带有一个后控制栅极
公开(公告)号：US08432216B2
公开(公告)日：2013-04-30
申请号：US13007483
申请日：2011-01-14
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G05F1/10 , H01L27/105 , G06F17/50
CPC分类号： H01L27/1203 , H01L29/78609 , H01L29/78648
摘要： The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells.
摘要翻译：本发明提供一种特别适用于其环境的数据通道单元，用于在绝缘体上半导体（SeOI）衬底上制造的集成电路中。数据通道单元包括场效应晶体管阵列，每个晶体管具有形成在SeOI衬底的薄半导体层中的源极区，漏极区和沟道区，并且还具有形成在栅极上的前栅极控制区渠道区域。特别地，数据通道单元的一个或多个晶体管还包括形成在沟道区下面的体衬底中的背栅极控制区域，并且被配置为根据其偏置状态来修改晶体管的性能特性。而且，包括一个或多个数据路径单元的集成电路以及用于设计或驱动这些数据路径单元的方法。

23. 发明申请

US20130015442A1 BONDED SEMICONDUCTOR STRUCTURES AND METHOD OF FORMING SAME 有权
标题翻译：粘结半导体结构及其形成方法
公开(公告)号：US20130015442A1
公开(公告)日：2013-01-17
申请号：US13637565
申请日：2011-02-22
申请人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
发明人： Carlos Mazure , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L29/04 , H01L29/06 , H01L21/302
CPC分类号： H01L27/0688 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/187 , H01L21/8221 , H01L2924/00011 , H01L2224/80001
摘要： Methods of forming semiconductor structures include transferring a portion (116a) of a donor structure to a processed semiconductor structure (102) that includes at least one non-planar surface. An amorphous film (144) may be formed over at least one non-planar surface of the bonded semiconductor structure, and the amorphous film may be planarized to form one or more planarized surfaces. Semiconductor structures include a bonded semiconductor structure having at least one non-planar surface, and an amorphous film disposed over the at least one non-planar surface. The bonded semiconductor structure may include a processed semiconductor structure and a portion of a single crystal donor structure attached to a non-planar surface of the processed semiconductor structure.
摘要翻译：形成半导体结构的方法包括将施主结构的部分（116a）转移到包括至少一个非平面表面的经处理的半导体结构（102）。可以在结合的半导体结构的至少一个非平面表面上形成非晶膜（144），并且可以将非晶膜平坦化以形成一个或多个平坦化表面。半导体结构包括具有至少一个非平面表面的键合半导体结构和设置在所述至少一个非平面表面上的非晶膜。键合的半导体结构可以包括处理的半导体结构和附接到处理的半导体结构的非平面表面的单晶体施主结构的一部分。

24. 发明授权

US08309426B2 Methods for manufacturing multilayer wafers with trench structures 有权
标题翻译：制造具有沟槽结构的多层晶圆的方法
公开(公告)号：US08309426B2
公开(公告)日：2012-11-13
申请号：US13093615
申请日：2011-04-25
申请人： Konstantin Bourdelle , Carlos Mazure
发明人： Konstantin Bourdelle , Carlos Mazure
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/76275 , H01L29/66181
摘要： The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.
摘要翻译：本发明提供了在多层晶片中制造沟槽结构的方法，该多层晶片包括衬底，衬底上的氧化物层和氧化物层上的半导体层。这些方法包括以下步骤：通过半导体层和氧化物层形成沟槽并延伸到衬底中，并且对所形成的沟槽进行退火处理，使得在沟槽的内表面处，半导体层的一些材料在至少暴露在沟槽内表面的部分氧化物层的一部分。根据本发明制造的衬底有利于制造各种半导体器件，例如MOSFET，沟槽电容器等。

25. 发明授权

US08305803B2 DRAM memory cell having a vertical bipolar injector 有权
标题翻译： DRAM存储单元具有垂直双极注入器
公开(公告)号：US08305803B2
公开(公告)日：2012-11-06
申请号：US12942754
申请日：2010-11-09
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G11C11/40 , G11C11/402
CPC分类号： H01L29/7841 , G11C11/404 , G11C2211/4016 , H01L27/0711 , H01L27/10802 , H01L29/086 , H01L29/7302
摘要： The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.
摘要翻译：本发明涉及具有源极，漏极和源极和漏极之间的浮体的FET晶体管的存储单元，以及可以被控制以将电荷注入到FET晶体管的浮动体中的注入器。注射器包括具有由FET晶体管的主体形成的发射极，基极和集电极的双极晶体管。具体地说，在存储单元中，双极型晶体管的发射极配置成使FET晶体管的源极作为双极晶体管的基极。本发明还包括包括根据本发明的第一方面的多个存储器单元的存储器阵列以及控制这种存储器单元的方法。

26. 发明授权

US08173512B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US08173512B2
公开(公告)日：2012-05-08
申请号：US13080436
申请日：2011-04-05
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/76
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
摘要翻译：一种用于形成在衬底上包括松弛或假松弛层的结构的方法。该方法包括在施主衬底上生长半导体材料的弹性应力层的步骤; 在应力层上形成粘性材料的玻璃状层; 去除供体衬底的一部分以形成包括玻璃层，应力层和供体衬底材料的表面层的结构; 图案化应力层; 并且在至少玻璃质层的粘度温度的温度下对结构进行热处理，以使应力层松弛以形成结构的松弛或假松弛层。

27. 发明申请

US20110287571A1 METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR 有权
标题翻译：制造背照明图像传感器的方法
公开(公告)号：US20110287571A1
公开(公告)日：2011-11-24
申请号：US13123661
申请日：2009-09-22
申请人： Konstantin Bourdelle , Carlos Mazure
发明人： Konstantin Bourdelle , Carlos Mazure
IPC分类号： H01L31/0376
CPC分类号： H01L27/14689 , H01L27/1464
摘要： A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.
摘要翻译：一种制造背照式图像传感器的方法，包括以下步骤：提供半导体层的第一衬底，特别是硅层，在半导体层上形成电子器件结构，然后仅仅掺杂半导体层。通过这样做，可以实现改进的光电二极管的掺杂剂分布和电性能，使得最终产品，即图像传感器具有更好的质量。

28. 发明申请

US20110241157A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：制造半导体基板的方法
公开(公告)号：US20110241157A1
公开(公告)日：2011-10-06
申请号：US12793515
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76254 , H01L21/187 , H01L21/2007 , H01L21/76251
摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.
摘要翻译：本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案，通过分子键合供体和手柄底物以获得供体 - 处理化合物。

29. 发明申请

US20110217825A1 FORMING STRUCTURES THAT INCLUDE A RELAXED OR PSEUDO-RELAXED LAYER ON A SUBSTRATE 有权
标题翻译：在基材上包含松散或松散层的形成结构
公开(公告)号：US20110217825A1
公开(公告)日：2011-09-08
申请号：US13080436
申请日：2011-04-05
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/762
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
摘要翻译：一种用于形成在衬底上包括松弛或假松弛层的结构的方法。该方法包括在施主衬底上生长半导体材料的弹性应力层的步骤; 在应力层上形成粘性材料的玻璃状层; 去除供体衬底的一部分以形成包括玻璃层，应力层和供体衬底材料的表面层的结构; 图案化应力层; 并且在至少玻璃质层的粘度温度的温度下对结构进行热处理，以使应力层松弛以形成结构的松弛或假松弛层。

30. 发明申请

US20110133822A1 DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER 有权
标题翻译：具有后控制门的SeOI基板上的数据路径电池绝缘层
公开(公告)号：US20110133822A1
公开(公告)日：2011-06-09
申请号：US13013580
申请日：2011-01-25
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： G05F1/10 , H01L27/105 , G06F17/50
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.
摘要翻译：本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区，，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。这种电路结构还包括连接背栅极控制区域的后栅极线。本发明还提供了操作和设计这种半导体器件结构的方法。

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