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1. 发明授权

US09035474B2 Method for manufacturing a semiconductor substrate 有权
标题翻译：半导体衬底的制造方法
公开(公告)号：US09035474B2
公开(公告)日：2015-05-19
申请号：US12793515
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
IPC分类号： H01L23/544 , H01L21/762 , H01L21/18 , H01L21/20
CPC分类号： H01L21/76254 , H01L21/187 , H01L21/2007 , H01L21/76251
摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.
摘要翻译：本发明涉及一种制造半导体衬底的方法，特别是通过提供一个施主衬底和一个把手衬底来制造绝缘体上半导体衬底，通常形成一个或多个掺杂区域的图案，通常在处理衬底内部，然后附着例如通过分子结合施主衬底和处理衬底以获得施主手柄化合物。

2. 发明申请

US20110241157A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：制造半导体基板的方法
公开(公告)号：US20110241157A1
公开(公告)日：2011-10-06
申请号：US12793515
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Konstantin Bourdelle , Bich-Yen Nguyen
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76254 , H01L21/187 , H01L21/2007 , H01L21/76251
摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.
摘要翻译：本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案，通过分子键合供体和手柄底物以获得供体 - 处理化合物。

3. 发明申请

US20100289113A1 FABRICATION PROCESS OF A HYBRID SEMICONDUCTOR SUBSTRATE 有权
标题翻译：混合半导体衬底的制造工艺
公开(公告)号：US20100289113A1
公开(公告)日：2010-11-18
申请号：US12726800
申请日：2010-03-18
申请人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
发明人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L21/2007 , H01L21/187 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L27/1207
摘要： The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.
摘要翻译：本发明涉及一种制造混合半导体衬底的方法，包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和SeOI层在绝缘层和体半导体区域之间，其中SeOI区域和体半导体区域共享相同的基底; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。从而避免了混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

4. 发明授权

US09018678B2 Method for forming a Ge on III/V-on-insulator structure 有权
标题翻译：用于在III / V绝缘体上形成Ge的方法
公开(公告)号：US09018678B2
公开(公告)日：2015-04-28
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/786 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

5. 发明申请

US20120228672A1 METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE 有权
标题翻译：用于形成III / V型绝缘体结构的方法
公开(公告)号：US20120228672A1
公开(公告)日：2012-09-13
申请号：US13399273
申请日：2012-02-17
申请人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
发明人： Nicolas Daval , Bich-Yen Nguyen , Cecile Aulnette , Konstantin Bourdelle
IPC分类号： H01L29/78 , H01L29/267 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/78681 , H01L21/76254 , H01L29/66742 , H01L29/78618 , H01L29/78684
摘要： The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.
摘要翻译：本发明涉及通过在施主衬底上生长放松的锗层来形成包含III / V材料的半导体层的半导体绝缘体结构的方法; 在锗层上生长至少一层III / V材料; 在松弛的锗层中形成裂开面; 将所述施主衬底的切割部分转移到支撑衬底，其中所述切割部分是在包括所述至少一层III / V材料的所述切割平面处切割的施主衬底的一部分。本发明还涉及III / V绝缘体上的锗结构，N场效应晶体管（NFET），NFET的制造方法，P场效应晶体管（PFET）及其制造方法 PFET。

6. 发明授权

US08058158B2 Hybrid semiconductor substrate including semiconductor-on-insulator region and method of making the same 有权
标题翻译：包括绝缘体上半导体区域的混合半导体衬底及其制造方法
公开(公告)号：US08058158B2
公开(公告)日：2011-11-15
申请号：US12726800
申请日：2010-03-18
申请人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
发明人： Konstantin Bourdelle , Bich-Yen Nguyen , Mariam Sadaka
IPC分类号： H01L21/425 , H01L21/70
CPC分类号： H01L21/2007 , H01L21/187 , H01L21/26513 , H01L21/823412 , H01L21/823481 , H01L27/1207
摘要： A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.
摘要翻译：一种用于制造混合半导体衬底的方法包括以下步骤：（a）提供包括绝缘体上半导体（SeOI）区域的混合半导体衬底，其包括在基底衬底上的绝缘层和绝缘层上的SeOI层，以及体半导体区域，其中所述SeOI区域和所述体半导体区域共享相同的基底基板; （b）在SeOI区域上提供掩模层; 和（c）通过同时掺杂SeOI区域和体半导体区域使得SeOI区域中的第一杂质水平包含在掩模内而形成第一杂质水平。因此，可以避免在混合半导体衬底的制造过程中涉及的更多数量的工艺步骤。

7. 发明授权

US07833877B2 Method for producing a semiconductor substrate 有权
标题翻译：半导体基板的制造方法
公开(公告)号：US07833877B2
公开(公告)日：2010-11-16
申请号：US11877456
申请日：2007-10-23
申请人： Konstantin Bourdelle , Carlos Mazure
发明人： Konstantin Bourdelle , Carlos Mazure
IPC分类号： H01L21/30
CPC分类号： H01L21/02667 , H01L21/2022 , H01L21/76254
摘要： This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer of material to form the thin layer comprises forming an amorphous layer in a part of the thin layer, and then recrystallizing the amorphous layer.
摘要翻译：本发明涉及一种通过将材料层从供体衬底转移到支撑衬底，然后通过移除材料层的一部分以形成薄层来制造衬底的方法。除去材料层的一部分以形成薄层的步骤包括在薄层的一部分中形成非晶层，然后使非晶层重结晶。

8. 发明申请

US20080014712A1 METHOD FOR DIRECT BONDING TWO SEMICONDUCTOR SUBSTRATES 有权
标题翻译：用于直接结合两个半导体衬底的方法
公开(公告)号：US20080014712A1
公开(公告)日：2008-01-17
申请号：US11624070
申请日：2007-01-17
申请人： Konstantin Bourdelle , Carlos Mazure , Olivier Rayssac , Pierre Rayssac , Gisele Rayssac
发明人： Konstantin Bourdelle , Carlos Mazure , Olivier Rayssac , Pierre Rayssac , Gisele Rayssac
IPC分类号： H01L21/30
CPC分类号： H01L21/187
摘要： The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.
摘要翻译：本发明提供了直接接合基底的方法，其中至少一个包括在其前表面或其附近延伸的半导体材料层。所提供的方法包括，在接合之前，使包含半导体材料的至少一个衬底的结合面在所选择的温度和选定的气体气氛中进行选择的热处理。键合的衬底可用于电子，光学或光电子应用。

9. 发明申请

US20060099779A1 Method for transferring a thin layer including a controlled disturbance of a crystalline structure 有权
标题翻译：用于转移包含晶体结构受控干扰的薄层的方法
公开(公告)号：US20060099779A1
公开(公告)日：2006-05-11
申请号：US11305444
申请日：2005-12-16
申请人： Ian Cayrefourcq , Carlos Mazure , Konstantin Bourdelle
发明人： Ian Cayrefourcq , Carlos Mazure , Konstantin Bourdelle
IPC分类号： H01L21/20 , H01L21/28
CPC分类号： H01L21/76254
摘要： The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface. One or several species are introduced into the thickness of the donor substrate to create the weakened zone, with the species being introduced with introduction parameters that are adjusted to introduce a maximum number of species at the zone of crystalline defects.
摘要翻译：本发明涉及一种从具有有序晶体结构的施主衬底向接收衬底转移薄有用层的方法。该方法包括在施主衬底中产生弱化区以限定要从供体衬底转移的层。施主衬底的表面区域的晶体结构受到干扰，从而在施主衬底的厚度内产生干扰的表面区域，从而限定受干扰的表面区域和施主衬底的下部区域之间的干扰界面，晶体结构保持不变。接下来，对施主衬底进行再结晶退火，以便从施主衬底的下部区域的结晶结构开始至少部分地重新结晶受阻区域，并在该平面内产生晶体缺陷区域扰动界面。将一个或多个物质引入施主衬底的厚度以产生弱化区域，其中引入物质，引入参数被调整以在晶体缺陷区域引入最大数量的物质。

10. 发明授权

US07799651B2 Method of treating interface defects in a substrate 有权
标题翻译：处理基材界面缺陷的方法
公开(公告)号：US07799651B2
公开(公告)日：2010-09-21
申请号：US12165365
申请日：2008-06-30
申请人： Carlos Mazure , Ian Cayrefourcq , Konstantin Bourdelle
发明人： Carlos Mazure , Ian Cayrefourcq , Konstantin Bourdelle
IPC分类号： H01L21/331
CPC分类号： H01L21/187 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L21/26506 , H01L21/324 , H01L21/76254 , H01L29/045
摘要： The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.
摘要翻译：本发明涉及一种处理由半导体材料制成的结构的方法，其中该结构包括限定具有缺陷的公共接口的第一和第二基板。所述方法包括形成称为所述无组织层的层，所述层包括所述界面，其中所述晶格的至少一部分被混杂; 并重新组织无组织层的晶格，以迫使缺陷更深地进入第一衬底。

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