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21. 发明授权

US06374367B1 Apparatus and method for monitoring a computer system to guide optimization 失效
标题翻译：用于监控计算机系统以引导优化的装置和方法
公开(公告)号：US06374367B1
公开(公告)日：2002-04-16
申请号：US08980124
申请日：1997-11-26
申请人： Jeffrey A. Dean , James E. Hicks, Jr. , George Z. Chrysos , Carl A. Waldspurger , William E. Weihl
发明人： Jeffrey A. Dean , James E. Hicks, Jr. , George Z. Chrysos , Carl A. Waldspurger , William E. Weihl
IPC分类号： H02H305
CPC分类号： G06F8/445 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected transactions are processed by the functional unit. The state information is analyzed to guide optimization.
摘要翻译：提供了一种用于对计算机系统的性能进行取样的方法。计算机系统包括多个功能单元。该方法选择要由计算机系统的特定功能单元处理的事务。当功能单元处理所选择的事务时，存储状态信息。分析状态信息以指导优化。

22. 发明授权

US06175814B1 Apparatus for determining the instantaneous average number of instructions processed 失效
标题翻译：用于确定处理的指令的瞬时平均数的装置
公开(公告)号：US06175814B1
公开(公告)日：2001-01-16
申请号：US08977438
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks, Jr. , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks, Jr. , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F900
CPC分类号： G06F11/3466 , G06F11/3452 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of a predetermined number (N) of clock cycles. The total number of instructions processed over the last P clock cycles is computed, where P is less than or equal to N. The total number of instructions processed is divided by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle. This average number of instructions processed is communicated to software.
摘要翻译：提供了一种用于在处理器时钟的时钟周期期间确定进入计算机系统的处理器流水线的阶段的平均数量的装置。在预定数量（N）个时钟周期的每一个期间，进入流水线的特定级的指令的数量被存储在队列中。计算在最后P个时钟周期中处理的指令总数，其中P小于或等于N。处理的指令的总数除以最后的P个处理器周期，以产生每个处理的指令的瞬时平均数处理器周期。处理的平均指令数量传达给软件。

23. 发明授权

US6000044A Apparatus for randomly sampling instructions in a processor pipeline 失效
标题翻译：用于在处理器流水线中随机采样指令的装置
公开(公告)号：US6000044A
公开(公告)日：1999-12-07
申请号：US980190
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/38 , G06F11/34 , G06F11/00
CPC分类号： G06F11/348 , G06F11/3466
摘要： An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
摘要翻译：提供了一种用于对系统的处理器流水线中的指令进行采样的装置。管道具有多个处理阶段。该装置包括用于将指令读取到管线的第一级中的取出单元。识别某些随机选择的指令，并且在特定选择的指令处于流水线的任何阶段时对系统的状态信息进行采样。当特定选择的指令离开管道时，通知软件，以便软件可以读取任何采样状态信息。

24. 发明授权

US5923872A Apparatus for sampling instruction operand or result values in a processor pipeline 失效
标题翻译：用于在处理器流水线中对指令操作数或结果值进行采样的装置
公开(公告)号：US5923872A
公开(公告)日：1999-07-13
申请号：US979848
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/38 , G06F11/34 , G06F9/00
CPC分类号： G06F11/348 , G06F11/3466
摘要： An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a particular selected instruction. Values of results computed during the processing of the particular selected instruction are recorded in a sampling record along with state information identifying the particular selected instruction. Software is informed whenever the particular selected instruction leaves the pipeline to read the recorded values and state information.
摘要翻译：提供了一种用于对系统的处理器流水线中的指令的操作数的值进行采样的装置，该管线具有多个处理级。指令被提取到管道的第一阶段。获取的指令中的任何一个被标识为特定的选择指令。在特定所选指令的处理期间计算的结果的值与标识特定所选指令的状态信息一起记录在采样记录中。当特定的选择指令离开管道以读取记录的值和状态信息时，通知软件。

25. 发明授权

US5809450A Method for estimating statistics of properties of instructions processed by a processor pipeline 失效
标题翻译：用于估计由处理器管线处理的指令的属性的统计的方法
公开(公告)号：US5809450A
公开(公告)日：1998-09-15
申请号：US979899
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/30 , G06F9/38 , G06F9/45 , G06F11/34 , G06F9/00
CPC分类号： G06F8/445 , G06F11/3409 , G06F11/3419 , G06F11/3452 , G06F11/3466 , G06F9/30101 , G06F9/383 , G06F9/384 , G06F9/3867 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method is provided for estimating statistics of properties of instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Some of the fetched instructions are randomly selected. State information of the system is recorded in a profile record as samples while the selected instruction are processed by the pipeline. The recorded state information is communiucated to software. The software statistically analyzes the recorded state information from a subset of the selected instructions to estimate the statistics of the instructions.
摘要翻译：提供了一种用于估计在计算机系统的流水线中处理的指令的属性的统计的方法，该管线具有多个处理阶段。指令被提取到管道的第一阶段。一些获取的指令是随机选择的。系统的状态信息作为采样记录在配置文件记录中，而所选择的指令由管道处理。记录的状态信息被通信给软件。该软件从所选指令的子集统计分析记录状态信息，以估计指令的统计。

26. 发明授权

US09430389B2 Prefetch with request for ownership without data 有权
标题翻译：预先获取所有权而无需数据
公开(公告)号：US09430389B2
公开(公告)日：2016-08-30
申请号：US13976429
申请日：2011-12-22
申请人： Jesus Corbal , Lisa K. Wu , George Z. Chrysos , Andrew T. Forsyth , Ramacharan Sundararaman
发明人： Jesus Corbal , Lisa K. Wu , George Z. Chrysos , Andrew T. Forsyth , Ramacharan Sundararaman
IPC分类号： G06F3/00 , G06F12/08 , G06F9/30
CPC分类号： G06F12/0815 , G06F9/30047 , G06F12/0811 , G06F12/0862
摘要： A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.
摘要翻译：描述由处理器执行的方法。该方法包括执行指令。该指令具有作为操作数的地址。指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。高速缓存行不在处理器的高速缓存中。所有权请求也表示高速缓存行不被发送到处理器。

27. 发明申请

US20140095831A1 APPARATUS AND METHOD FOR EFFICIENT GATHER AND SCATTER OPERATIONS 有权
标题翻译：高效和高效运行的装置和方法
公开(公告)号：US20140095831A1
公开(公告)日：2014-04-03
申请号：US13631071
申请日：2012-09-28
申请人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
发明人： Edward T. Grochowski , Dennis R. Bradford , George Z. Chrysos , Andrew T. Forsyth , Michael D. Upton , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/355
摘要： An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.
摘要翻译：描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。

28. 发明授权

US08407421B2 Cache spill management techniques using cache spill prediction 失效
标题翻译：缓存溢出管理技术使用缓存溢出预测
公开(公告)号：US08407421B2
公开(公告)日：2013-03-26
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, Jr. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

29. 发明申请

US20110145501A1 CACHE SPILL MANAGEMENT TECHNIQUES 失效
标题翻译：缓存溢出管理技术
公开(公告)号：US20110145501A1
公开(公告)日：2011-06-16
申请号：US12639214
申请日：2009-12-16
申请人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
发明人： Simon C. Steely, JR. , William C. Hasenplaugh , Aamer Jaleel , George Z. Chrysos
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0806 , G06F12/12
摘要： An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful cache lines from a source cache are intelligently selected for spill. Furthermore, another learning mechanism—cache spill prediction—may be implemented separately or in conjunction with usefulness prediction. The cache spill prediction is capable of learning the effectiveness of remote caches at holding spilled cache lines for the source cache. As a result, cache lines are capable of being intelligently selected for spill and intelligently distributed among remote caches based on the effectiveness of each remote cache in holding spilled cache lines for the source cache.
摘要翻译：这里描述了用于智能地溢出高速缓存行的装置和方法。了解先前从源缓存溢出的高速缓存行的有用性，从而智能地选择来自源缓存的随后驱逐的溢出。此外，另一种学习机制 - 缓存溢出预测 - 可以单独实施或结合有用性预测来实现。高速缓存溢出预测能够学习在为源缓存保留溢出的高速缓存行时远程高速缓存的有效性。因此，基于每个远程高速缓存在保存用于源高速缓存的溢出高速缓存行的有效性的情况下，高速缓存行能够被智能地选择为溢出并且智能地分布在远程高速缓存中。

30. 发明授权

US07844801B2 Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors 有权
标题翻译：芯片多处理器中亲和力引导的投机辅助线程的方法和装置
公开(公告)号：US07844801B2
公开(公告)日：2010-11-30
申请号：US10632431
申请日：2003-07-31
申请人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
发明人： Hong Wang , Perry H. Wang , Jeffery A. Brown , Per Hammarlund , George Z. Chrysos , Doron Orenstein , Steve Shih-wei Liao , John P. Shen
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3851 , G06F12/0862
摘要： Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.
摘要翻译：提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。由辅助线程预取的数据被提供给辅助核心。对于一个实施例，由辅助线程预取的数据被推送到主核心。它也可以也可以不被提供给辅助核心。在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

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