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1. 发明授权

US6000044A Apparatus for randomly sampling instructions in a processor pipeline 失效
标题翻译：用于在处理器流水线中随机采样指令的装置
公开(公告)号：US6000044A
公开(公告)日：1999-12-07
申请号：US980190
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/38 , G06F11/34 , G06F11/00
CPC分类号： G06F11/348 , G06F11/3466
摘要： An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are identified, and state information of the system is sampled while a particular selected instruction is in any stage of the pipeline. Software is informed when the particular selected instruction leaves the pipeline so that the software can read any of the sampled state information.
摘要翻译：提供了一种用于对系统的处理器流水线中的指令进行采样的装置。管道具有多个处理阶段。该装置包括用于将指令读取到管线的第一级中的取出单元。识别某些随机选择的指令，并且在特定选择的指令处于流水线的任何阶段时对系统的状态信息进行采样。当特定选择的指令离开管道时，通知软件，以便软件可以读取任何采样状态信息。

2. 发明授权

US06195748B1 Apparatus for sampling instruction execution information in a processor pipeline 失效
标题翻译：用于在处理器流水线中对指令执行信息进行采样的装置
公开(公告)号：US06195748B1
公开(公告)日：2001-02-27
申请号：US08979033
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl , Daniel L. Leibholz , Edward J. McLellan
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Carl A. Waldspurger , William E. Weihl , Daniel L. Leibholz , Edward J. McLellan
IPC分类号： G06F1100
CPC分类号： G06F9/30101 , G06F9/3861 , G06F9/3867
摘要： An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latency, and state information of the system is sampled while any of the selected instructions are in any stage of the pipeline. Software is informed whenever any of the selected instructions leaves the pipeline to read the event and latency information.
摘要翻译：提供了一种用于对计算机系统的处理器流水线中的指令进行采样的装置。管道具有多个处理阶段。指令被提取到管道的第一阶段。获取的指令的子集被标识为所选择的指令。系统的事件，延迟和状态信息被采样，而任何所选择的指令都处于流水线的任何阶段。当任何选定的指令离开管道以读取事件和延迟信息时，通知软件。

3. 发明授权

US6163840A Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline 失效
标题翻译：用于在处理器流水线中采样多个潜在并发指令的方法和装置
公开(公告)号：US6163840A
公开(公告)日：2000-12-19
申请号：US980168
申请日：1997-11-26
申请人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
发明人： George Z. Chrysos , Jeffrey Dean , James E. Hicks , Daniel L. Leibholz , Edward J. McLellan , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/38 , G06F11/34 , G06F9/000
CPC分类号： G06F11/348 , G06F11/3466
摘要： An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.
摘要翻译：提供了一种用于在系统的处理器流水线中采样多个并发执行指令的装置。管道具有多个处理阶段。当指令被提取到流水线的第一级时，该装置识别所选择的多个。所选择的多个指令的子集在管道中并发执行。系统的状态信息被采样，而多个选择的指令中的任何一个处于流水线的任何阶段。只要所有选定的指令离开管道，软件才能通知软件，以便软件可以读取任何状态信息。

4. 发明授权

US5394428A Controlled, high-power laser oscillator 失效
标题翻译：受控的大功率激光振荡器
公开(公告)号：US5394428A
公开(公告)日：1995-02-28
申请号：US27417
申请日：1993-03-08
申请人： Edward J. McLellan
发明人： Edward J. McLellan
IPC分类号： H01S3/08 , H01S3/106
CPC分类号： H01S3/106 , H01S3/08059 , H01S3/08081 , H01S3/08068
摘要： Controlled, high-power laser oscillator. A single laser gain medium is used to efficiently generate high-power, controlled laser light without exposing the control elements to high-power radiation. The control element or elements are separated from the oscillator gain volume by a separator optic which permits only a portion of the energy from the gain volume to enter the region of the control elements, laser light having the desired characteristics being returned to the gain volume through the separator optic. Energy not entering the control region exits the laser as oscillator output energy in order to obtain high efficiency.
摘要翻译：受控的大功率激光振荡器。单个激光增益介质用于有效地产生高功率，受控的激光，而不会将控制元件暴露于高功率辐射。通过分离器光学器件将控制元件与振荡器增益体积分开，分离器光学器件仅允许来自增益体积的能量的一部分进入控制元件的区域，具有期望特性的激光通过分离器光学元件。无法进入控制区的能量作为振荡器输出能量退出激光，以获得高效率。

5. 发明授权

US5088104A Multiple discharge gas laser apparatus 失效
标题翻译：多重放电气体激光装置
公开(公告)号：US5088104A
公开(公告)日：1992-02-11
申请号：US375250
申请日：1989-07-03
申请人： Edward J. McLellan
发明人： Edward J. McLellan
IPC分类号： H01S3/07 , H01S3/097 , H01S3/101 , H01S3/104
CPC分类号： H01S3/076 , H01S3/097 , H01S3/101 , H01S3/104 , H01S3/09702
摘要： Multiple discharge gas laser apparatus. A compact apparatus for simultaneously or individually generating a plurality of laser output beams in a selected pattern suitable for marking objects, for communications, or for remote chemical sensing or other remote sensing applications, among other uses, where all of the electrodes providing lasing gas excitation are located in a single gas volume and share a single output coupler is described. In this manner, all of the output beams are parallel in far field, to the extent variations in mode structure permit, without the necessity of undertaking detailed optical adjustments. Moreover, the focal plane of the output laser radiation is insensitive to significant positional variation of focusing optics utilized to increase the intensity thereof for marking purposes. Electrodes can be utilized for more than one discharge; that is, the direction of the discharge can be selected to involve any adjacent electrode having opposite charge polarity.
摘要翻译：多重放电气体激光装置。一种紧凑的装置，用于同时或单独产生多种激光输出光束，其中所选择的图案适合于标记物体，用于通信，或用于远程化学感测或其他遥感应用以及其它用途，其中所有电极提供激发气体激发位于单个气体体积中并且共享单个输出耦合器被描述。以这种方式，所有输出光束在远场平行，在模式结构允许的范围内，而不需要进行详细的光学调整。此外，输出激光辐射的焦平面对于用于增加其用于标记目的的强度的聚焦光学器件的显着位置变化不敏感。电极可用于多次放电; 也就是说，可以选择放电的方向以涉及具有相反电荷极性的任何相邻电极。

6. 发明授权

US4412333A Three-electrode low pressure discharge apparatus and method for uniform ionization of gaseous media 失效
标题翻译：三电极低压放电装置及气态介质均匀电离的方法
公开(公告)号：US4412333A
公开(公告)日：1983-10-25
申请号：US198028
申请日：1980-10-17
申请人： Edward J. McLellan
发明人： Edward J. McLellan
IPC分类号： H01S3/038 , H01S3/0971 , H01S3/097
CPC分类号： H01S3/038 , H01S3/09713
摘要： Uniform, transverse electrical discharges are produced in gaseous media without the necessity of switching the main discharge voltage with an external device which carries the entire discharge current. A three-electrode low pressure discharge tube is charged across its anode (1) and cathode (2) to below breakdown voltage using a dc voltage source (3). An array of resistors (4) or capacitors can be made to discharge to the wire screen anode by means of a low energy high voltage pulse circuit (5) producing sufficient preionization in the region between the anode and cathode to initiate and control the main discharge. The invention has been demonstrated to be useful as a CO.sub.2 laser oscillator and pulse-smoother. It can be reliably operated in the sealed-off mode.
摘要翻译：在气体介质中产生均匀的横向放电，而不需要用承载整个放电电流的外部装置切换主放电电压。使用直流电压源（3）将三极低压放电管的阳极（1）和阴极（2）充电至低于击穿电压。可以通过在阳极和阴极之间的区域中产生足够的预电离的低能量高压脉冲电路（5），使电阻器（4）或电容器阵列排放到丝网阳极，以启动和控制主放电。本发明已被证明可用作CO 2激光振荡器和脉冲平滑器。它可以在密封模式下可靠地工作。

7. 发明申请

US20120166777A1 METHOD AND APPARATUS FOR SWITCHING THREADS 审中-公开
标题翻译：用于切换螺纹的方法和装置
公开(公告)号：US20120166777A1
公开(公告)日：2012-06-28
申请号：US12976034
申请日：2010-12-22
申请人： Edward J. McLellan , Magiting M. Talisayon , Donald A. Priore
发明人： Edward J. McLellan , Magiting M. Talisayon , Donald A. Priore
IPC分类号： G06F9/30
CPC分类号： G06F9/226 , G06F9/3851
摘要： Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur.
摘要翻译：公开了一种用于在包括共享微代码引擎的多个处理器核心的处理器中切换或停放线程的技术。在双核或多核系统中，处理器核心的前端（例如，微代码引擎）可以由两个或更多个主动线程共享，以便减少面积，成本等。当正在运行的线程可能被置于睡眠状态，并且当当前线程正在运行时，当产生微代码命令发生时，可以启动另一线程的执行。可以在第二线程进入睡眠状态，产生，退出处理等的情况下恢复线程。或者，当睡眠微代码命令发出时，可以将线程置于睡眠状态，当睡眠微代码命令被编程为发生时，线程需要等待发生事件。

8. 发明授权

US07100020B1 Digital communications processor 有权
标题翻译：数字通讯处理器
公开(公告)号：US07100020B1
公开(公告)日：2006-08-29
申请号：US09674864
申请日：1999-05-07
申请人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
发明人： Thomas B. Brightman , Andrew T. Brown , John F. Brown , James A. Farrell , Andrew D. Funk , David J. Husak , Edward J. McLellan , Mark A. Sankey , Paul Schmitt , Donald A. Priore
IPC分类号： G06F15/00
CPC分类号： H04L49/10 , H04L49/254 , H04L49/3009 , H04L49/3036
摘要： An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.
摘要翻译：一种集成电路（203），用于一般地处理数据流和特别是数据包流。集成电路（203）包括多个分组处理器（307,313,303），表查找引擎（301），队列管理引擎（305）和缓冲器管理引擎（315）。分组处理器（307,313,303）包括接收处理器（421），发射处理器（427）和芯片处理器（401），所有这些都是可编程的。接收处理器（421）和核心处理器（401）协作以接收和路由正在接收的分组，并且核心处理器（401）和发射处理器（427）协作传送分组。通过使用来自表查找引擎（301）的信息来确定队列管理引擎（305）中要接收描述所接收的分组的有效载荷的描述符（217）的队列（215）来完成路由。

9. 发明授权

US06449713B1 Implementation of a conditional move instruction in an out-of-order processor 有权
标题翻译：在乱序处理器中实现条件移动指令
公开(公告)号：US06449713B1
公开(公告)日：2002-09-10
申请号：US09195121
申请日：1998-11-18
申请人： Joel Springer Emer , Bruce Edwards , Daniel Lawrence Leibholz , Edward J. McLellan , Derrick R. Meyer
发明人： Joel Springer Emer , Bruce Edwards , Daniel Lawrence Leibholz , Edward J. McLellan , Derrick R. Meyer
IPC分类号： G06F900
CPC分类号： G06F9/30094 , G06F9/30032 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3017
摘要： A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The technique further involves replacing the conditional move instruction within the instruction stream with the generated multiple instructions. The generated multiple instructions are generated such that each of the generated multiple instructions executes using no more than two input ports of an execution unit. The generated multiple instructions include a first generated instruction that produces a condition result indicating whether a condition exists, and a second generated instruction that inputs the condition result as a portion of an operand which identifies a register of the out-of-order data processor. The second generated instruction performs a first move operation when the condition is determined to exist, and a second move operation when the condition is determined not to exist.
摘要翻译：用于处理乱序数据处理器中的条件移动指令的技术。该技术涉及检测指令流内的条件移动指令，并根据检测到的条件移动指令生成多条指令。该技术还包括用生成的多个指令来替换指令流内的条件移动指令。生成的多个指令被生成，使得每个生成的多个指令使用执行单元的不超过两个输入端口来执行。所生成的多个指令包括产生指示条件是否存在的条件结果的第一生成指令，以及输入条件结果作为识别无序数据处理器的寄存器的操作数的一部分的第二生成指令。当所述条件被确定为存在时，所述第二生成指令执行第一移动操作，以及当所述条件不存在时进行第二移动操作。

10. 发明授权

US6081887A System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction 失效
标题翻译：用于向前传递每个预测的索引值的系统，以使真实预测器能够将真值与特定分支指令相关联
公开(公告)号：US6081887A
公开(公告)日：2000-06-27
申请号：US191869
申请日：1998-11-12
申请人： Simon C. Steely, Jr. , Edward J. McLellan , Joel S. Emer
发明人： Simon C. Steely, Jr. , Edward J. McLellan , Joel S. Emer
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3844
摘要： A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor is accessible in one instruction cycle, and therefore provides minimum predictor latency. Update latency is minimized by storing multiple predictions in the front end stored predictor which are indexed by an index counter. The multiple predictions, as provided by the back end, are indexed by the index counter to select a particular one as current prediction on a given instruction pipeline cycle. The front end stored predictor also passes along to the back end predictor, such as through the instruction pipeline, a position value used to generate the predictions. This further structure accommodates ghost branch instructions that turn out to be flushed out of the pipeline when it must be backed up. As a result, the front end always provides an accurate prediction with minimum update latency.
摘要翻译：一种用于预测与具有指令流水线的处理器一起使用的条件转移指令的结果的技术。存储的预测器连接到管道的前端，并且从连接到管道后端的基于真实的预测器训练。存储的预测器可以在一个指令周期中访问，因此提供最小预测器延迟。通过将多个预测存储在由索引计数器索引的前端存储的预测器中来最小化更新延迟。由后端提供的多个预测由索引计数器索引，以选择特定的预测作为给定指令流水线周期上的当前预测。前端存储的预测器还将传递到后端预测器，例如通过指令流水线，用于产生预测的位置值。这种进一步的结构可以容纳重影分支指令，当它必须被备份时，这些指令将被清除流出管道。因此，前端总是以最小的更新延迟提供准确的预测。

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