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21. 发明授权

US06831860B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06831860B2
公开(公告)日：2004-12-14
申请号：US09997080
申请日：2001-11-28
申请人： Byeong-Hoon Lee , Seung-Keun Lee
发明人： Byeong-Hoon Lee , Seung-Keun Lee
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/08
摘要： A sector structure of a flash memory device minimizes a layout area in a chip without deteriorating a high-speed operation. The sector structure of the flash memory device includes a plurality of sectors, each sector including memory cell transistors in a cell array block sharing a common bulk region with transistors in a column decoder block.
摘要翻译：闪存器件的扇区结构使芯片中的布局区域最小化，而不会降低高速操作。闪存器件的扇区结构包括多个扇区，每个扇区包括与列解码器块中的晶体管共享公共体区的单元阵列块中的存储单元晶体管。

22. 发明授权

US06781904B2 Low-voltage semiconductor memory device 失效
标题翻译：低压半导体存储器件
公开(公告)号：US06781904B2
公开(公告)日：2004-08-24
申请号：US10357538
申请日：2003-02-03
申请人： Seung-Keun Lee , Young-Ho Lim
发明人： Seung-Keun Lee , Young-Ho Lim
IPC分类号： G11C702
CPC分类号： G11C16/24 , G11C7/12 , G11C16/0416
摘要： This invention provides a semiconductor memory device operating at a low operating voltage (e.g., 1.8 V) and the semiconductor memory device includes a discharge circuit for discharging a voltage of a bit line prior to read/write operations. The discharge circuit includes high-voltage and low-voltage transistors coupled in series between the bit line and a reference voltage. The high-voltage transistor is switched on and off by a high voltage and the low-voltage transistor is switched on and off by a discharge signal.
摘要翻译：本发明提供了在低工作电压（例如1.8V）下工作的半导体存储器件，并且半导体存储器件包括用于在读/写操作之前放电位线的电压的放电电路。放电电路包括串联在位线和参考电压之间的高压和低压晶体管。高电压晶体管由高电压接通和断开，低压晶体管通过放电信号导通和截止。

23. 发明授权

US06587375B2 Row decoder for a nonvolatile memory device 失效
公开(公告)号：US06587375B2
公开(公告)日：2003-07-01
申请号：US09923718
申请日：2001-08-06
申请人： Hwi-Taek Chung , Seung-Keun Lee , Young-Ho Lim
发明人： Hwi-Taek Chung , Seung-Keun Lee , Young-Ho Lim
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/10
摘要： The invention provides decoder circuits for selecting a word line in a semiconductor memory device which comprises a plurality of memory cell sectors including a plurality of word lines and bit lines and a plurality of memory cells which each is electrically erasable and programmable. The decoder circuits comprise a pull-up and pull-down transistors connected to global word lines which are connected to the word lines via connecting means, the decoder circuits turning on pull-down transistors before a high voltage according to an operation mode is supplied to one selected from the global word lines and pre-charging the gates of the pull-up transistors to the high voltage. The invention enables the decoder circuits to supply the word line drive voltage to the global word lines connected to memory cells by using the self-boosting method to thereby reduce the boosting load.

24. 发明授权

US5986947A Charge pump circuits having floating wells 失效
标题翻译：具有浮动井的电荷泵电路
公开(公告)号：US5986947A
公开(公告)日：1999-11-16
申请号：US57784
申请日：1998-04-09
申请人： Ki-Hwan Choi , Seung-Keun Lee , Kang-Deog Suh
发明人： Ki-Hwan Choi , Seung-Keun Lee , Kang-Deog Suh
IPC分类号： G11C16/06 , G11C5/14 , G11C16/12 , H02M3/07 , G11C7/00
CPC分类号： G11C16/12 , G11C5/145 , H02M3/073
摘要： The well regions of pumping units of charge pump circuits are maintained electrically floating. By maintaining the wells electrically floating, reduced impact from the body effect may be obtained. More specifically, integrated circuit charge pump circuits boost a first voltage from a voltage source to a second voltage at an output terminal. The charge pump circuits include a plurality of pumping units in an integrated circuit substrate of first conductivity type, that are serially connected between the voltage source and the output terminal. Each of the pumping units includes a well region of second conductivity type in the integrated circuit substrate of first conductivity type. The well region of second conductivity type is electrically floating. Each pumping unit also includes a transistor of the first conductivity type in the floating well region of second conductivity type, and a capacitor that is electrically connected to the transistor of the first conductivity type in the floating well region of second conductivity type.
摘要翻译：电荷泵电路的泵浦单元的阱区保持电浮动。通过维持井电浮动，可以获得来自身体效应的减小的冲击。更具体地，集成电路电荷泵电路在输出端将电压源的第一电压提升到第二电压。电荷泵电路包括在第一导电类型的集成电路衬底中的多个泵送单元，其串联连接在电压源和输出端子之间。每个泵送单元在第一导电类型的集成电路基板中包括第二导电类型的阱区域。第二导电类型的阱区域是电浮动的。每个泵送单元还包括在第二导电类型的浮动阱区域中的第一导电类型的晶体管，以及在第二导电类型的浮动阱区域中电连接到第一导电类型的晶体管的电容器。

25. 发明授权

US07428169B2 Nonvolatile semiconductor memory device and voltage generating circuit for the same 失效
标题翻译：非易失性半导体存储器件和电压产生电路相同
公开(公告)号：US07428169B2
公开(公告)日：2008-09-23
申请号：US11262759
申请日：2005-11-01
申请人： Doo-Sub Lee , Seung-Keun Lee
发明人： Doo-Sub Lee , Seung-Keun Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/30
摘要： A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.
摘要翻译：非易失性半导体存储器件包括多个存储器单元的存储单元阵列; 以及用于产生要施加到存储单元的编程电压的电压产生电路。电压产生电路包括：第一电压产生单元，用于通过第一电荷泵产生负电压; 以及用于通过第二电荷泵产生正电压的第二电压产生单元。在加速编程操作期间，第一电压产生单元使用外部电源电压提高第一电荷泵的泵送效率，并且第二电压产生单元直接输出外部电源电压。

26. 发明授权

US07352618B2 Multi-level cell memory device and associated read method 有权
标题翻译：多级单元存储器件及相关读取方法
公开(公告)号：US07352618B2
公开(公告)日：2008-04-01
申请号：US11296476
申请日：2005-12-08
申请人： Dae-Han Kim , Seung-Keun Lee
发明人： Dae-Han Kim , Seung-Keun Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/24
摘要： A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.
摘要翻译： NOR闪存器件包括适于存储至少两位数据的存储器单元。通过产生具有第一幅度的参考电流来对存储器单元执行读取操作，以检测最高有效位（MSB）的值并产生具有第二幅度的参考电流以检测最低有效位（LSB）的值）。通过在读取操作期间将第一和第二参考电流与流过存储器单元的电流量进行比较来检测MSB和LSB的相应值。第一和第二参考电流的相应大小由参考电压发生器产生的不同参考电压确定。

27. 发明授权

US07271436B2 Flash memory devices including a pass transistor 有权
标题翻译：包括传输晶体管的闪存器件
公开(公告)号：US07271436B2
公开(公告)日：2007-09-18
申请号：US11021232
申请日：2004-12-23
申请人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
发明人： Chang-Hyun Lee , Sang-Pil Sim , Seung-Keun Lee
IPC分类号： H01L29/76 , H01L29/788 , H01L29/94 , H01L31/00
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.
摘要翻译：闪存集成电路器件包括集成电路基板。集成电路基板上的单元阵列包括多个单元晶体管。位线耦合到多个单元晶体管中的一个，并且第一传输晶体管耦合到位线。第一传输晶体管具有第一扩散结构，其被配置为提供比第二扩散结构高的击穿电压。一个或多个第二传输晶体管耦合到第一传输晶体管。第二传输晶体管具有第二扩散结构。第二扩散结构可以具有小于第一扩散结构的电阻的电阻。

28. 发明授权

US07082058B2 Non-volatile semiconductor memory device having sense amplifier with increased speed 有权
标题翻译：具有增加速度的读出放大器的非易失性半导体存储器件
公开(公告)号：US07082058B2
公开(公告)日：2006-07-25
申请号：US10991042
申请日：2004-11-16
申请人： Seung-Keun Lee , Jin-Sung Park
发明人： Seung-Keun Lee , Jin-Sung Park
IPC分类号： G11C11/34
CPC分类号： G11C16/28
摘要： In the non-volatile semiconductor memory device having a sense amplifier for sensing data stored in a selected memory cell by comparing cell current differences from a reference cell, a current sink unit coupled in parallel with a reference line and a data line are provided. The reference line connects between the reference cell and the sense amplifier, and the data line connects between the selected memory cell and the sense amplifier, where the current sink unit together increases currents of the reference line and the data line. Also, the device includes a sink current control unit having a configuration of a current mirror with the current sink unit, the sink current control unit consisting of a switching unit and being for controlling a sink current of the current sink unit. The device improves data sensing speed and controls sensing current in conformity with the characteristics of a memory cell.
摘要翻译：在具有读出放大器的非易失性半导体存储器件中，提供了用于通过比较来自参考单元的单元电流差异来感测存储在所选存储单元中的数据的读出放大器，提供与参考线和数据线并联耦合的电流宿单元。参考线连接在参考单元和读出放大器之间，数据线连接在所选择的存储单元和读出放大器之间，其中电流吸收单元一起增加参考线和数据线的电流。此外，该装置包括具有电流反射镜与电流吸收单元的配置的宿电流控制单元，宿电流控制单元由开关单元组成并用于控制电流宿单元的宿电流。该器件提高了数据感测速度，并根据存储单元的特性来控制感应电流。

29. 发明申请

US20060126385A1 Flash memory device with burst read mode of operation 失效
标题翻译：具有突发读取操作模式的闪存设备
公开(公告)号：US20060126385A1
公开(公告)日：2006-06-15
申请号：US11345995
申请日：2006-02-01
申请人： Seung-Keun Lee , Jin-Sung Park
发明人： Seung-Keun Lee , Jin-Sung Park
IPC分类号： G11C16/04
CPC分类号： G11C7/1027 , G11C7/12 , G11C7/18 , G11C16/24 , G11C16/26 , G11C2207/005
摘要： A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.
摘要翻译：公开了一种闪存器件，其包括多个列，每个列与多个存储器单元连接。列选择器电路响应于列地址选择列的一部分，并且多个读出放大器组通过列选择器电路与所选择的列连接。列选择器电路根据列地址是否4N对齐（其中N是具有1或更大的值的整数）可变地选择列。例如，当列地址为4N对齐时，列选择器电路选择列地址的列，并且当列地址不是4N对齐时选择列列地址的列。

30. 发明申请

US20060120196A1 Trimming circuits including isolated well regions and related memory devices 审中-公开
标题翻译：微调电路包括隔离阱区和相关的存储器件
公开(公告)号：US20060120196A1
公开(公告)日：2006-06-08
申请号：US11240236
申请日：2005-09-30
申请人： Hong-Soo Jeon , Seung-Keun Lee
发明人： Hong-Soo Jeon , Seung-Keun Lee
IPC分类号： G11C5/14
CPC分类号： G11C16/30
摘要： A trimming circuit may include a plurality of resistors coupled in series between an output node and a reference voltage, and a plurality of transistors. More particularly, each transistor of the plurality of transistors may be electrically coupled in parallel with a respective one of the resistors. Moreover, each of the transistors may include a respective well region, and well regions of different transistors may be isolated. Related memory devices are also discussed.
摘要翻译：修整电路可以包括串联耦合在输出节点和参考电压之间的多个电阻器和多个晶体管。更具体地，多个晶体管中的每个晶体管可以与相应的一个电阻器并联电耦合。此外，每个晶体管可以包括相应的阱区，并且可以隔离不同晶体管的阱区。还讨论了相关的存储器件。

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