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21. 发明授权

US08135752B2 Deleting leaves in tree table structures 失效
标题翻译：删除树表结构中的树叶
公开(公告)号：US08135752B2
公开(公告)日：2012-03-13
申请号：US12350493
申请日：2009-01-08
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
IPC分类号： G06F7/00 , G06F17/00 , G06F17/30
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a patricia tree having leaf keys and pattern search control blocks containing a prefix and either an end-of-trail leaf or a pointer to another of the pattern search control blocks, by placing each of the prefixes in a tree prefix table; searching for a key in the tree; searching for the key in the prefix table if the tree searching does not find the key in the tree; confirming that the key is deleted if the key is not found in the prefix table; deleting the key from one of the pattern search control blocks; and collapsing the patricia tree by eliminating the left most pattern search control block from the patricia tree if the patricia tree searching finds the key.
摘要翻译：提供的技术和制品包括计算机可读程序，当在计算机上执行计算机可读程序时，使计算机从具有叶键的图案搜索控制块和包含前缀的叶片的叶片中删除叶或指向另一个模式搜索控制块的指针，通过将每个前缀放置在树前缀表中; 在树中搜索一个键; 如果树搜索没有在树中找到密钥，则在前缀表中搜索密钥; 如果在前缀表中没有找到密钥，则确认该密钥被删除; 从模式搜索控制块之一删除密钥; 并且如果所述爱好者树搜索找到所述密钥，则通过从所述爱好树中消除所述最左图案搜索控制块来折叠所述爱好者树。

22. 发明授权

US07702630B2 Longest prefix match lookup using hash function 失效
标题翻译：使用哈希函数的最长前缀匹配查找
公开(公告)号：US07702630B2
公开(公告)日：2010-04-20
申请号：US11353841
申请日：2006-02-14
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Piyush C. Patel
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Piyush C. Patel
IPC分类号： G06F7/00
CPC分类号： H04L45/00 , G06F17/30985 , H04L12/66 , H04L45/745 , H04L45/7457 , Y10S707/99933 , Y10S707/99935 , Y10S707/99936
摘要： A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.
摘要翻译：当在网络处理器的路由表结构中搜索直接表时，使用方法和装置来在可变长度前缀搜索中找到最长的前缀匹配。通过路由表结构的搜索是通过用互联网协议地址的第一段与虚拟专用网络号进行散列加速，然后将IP地址的未分配比特连接到散列操作的结果以形成输入密钥。模式一次比较一点，直到找到完全匹配或最佳匹配。搜索在搜索树中进行，其提供匹配结果将是最佳匹配。

23. 发明授权

US08250348B2 Methods and apparatus for dynamically switching processor mode 有权
标题翻译：用于动态切换处理器模式的方法和装置
公开(公告)号：US08250348B2
公开(公告)日：2012-08-21
申请号：US11132658
申请日：2005-05-19
申请人： Gordon T. Davis , Jeffrey H. Derby
发明人： Gordon T. Davis , Jeffrey H. Derby
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F9/46
CPC分类号： G06F9/3017
摘要： In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一处理方法。第一处理方法包括以下步骤：（1）基于与由处理器接收的第一指令相关联的操作数大小，以第一模式操作处理器; 和（2）基于与由处理器接收的第二指令相关联的不同操作数大小，将处理器操作模式从第一模式动态地切换到第二模式。提供了许多其他方面。

24. 发明授权

US07984263B2 Structure for a memory-centric page table walker 有权
标题翻译：以内存为中心的页表步行器的结构
公开(公告)号：US07984263B2
公开(公告)日：2011-07-19
申请号：US12109671
申请日：2008-04-25
申请人： Sumedh W. Sathaye , Gordon T. Davis
发明人： Sumedh W. Sathaye , Gordon T. Davis
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F12/0888 , G06F12/1027
摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.
摘要翻译：提供了一种体现在用于设计，制造和测试设计中的至少一个的机器可读存储介质中的设计结构。设计结构包括页表步行器。页表助行器从与数据处理器相关联的存储器管理单元中的常规位置移动到主存储器（即主存储器控制器）中的位置。结果，其中对数据请求的处理可以选择性地避免或绕过与数据处理器相关联的麻烦的高速缓存。

25. 发明授权

US07644233B2 Apparatus and method for supporting simultaneous storage of trace and standard cache lines 有权
标题翻译：用于支持跟踪标准缓存行的同时存储的装置和方法
公开(公告)号：US07644233B2
公开(公告)日：2010-01-05
申请号：US11538445
申请日：2006-10-04
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

26. 发明授权

US5586273A HDLC asynchronous to synchronous converter 失效
公开(公告)号：US5586273A
公开(公告)日：1996-12-17
申请号：US292563
申请日：1994-08-18
申请人： Dana L. Blair , Gordon T. Davis , Cloyd S. McIlvaine
发明人： Dana L. Blair , Gordon T. Davis , Cloyd S. McIlvaine
IPC分类号： H04L29/06 , H04L29/08 , H04Q11/04 , G06F13/00
CPC分类号： H04Q11/0457 , H04L29/06 , H04L69/08 , H04L69/324 , H04Q2213/13093 , H04Q2213/13103 , H04Q2213/13199 , H04Q2213/13202 , H04Q2213/13204 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/13361 , H04Q2213/13362
摘要： Communication, using a synchronous protocol, over a synchronous communications link, between synchronous application programs executed on a terminal (i.e., personal computer, PC) with an asynchronous byte-oriented interface and a PC with a synchronous frame orientated interface is made possible by enhancing the PC with the asynchronous byte-oriented interface with a device which modifies the data to be transmitted by inserting framing flags and transparency characters before the data passes through the COMM port (asynchronous byte-oriented interface) and extracting the transparency characters after the data exits the COMM port. As a consequence, the PC with the frame-oriented interface does not have to be modified.

27. 发明授权

US4991169A Real-time digital signal processing relative to multiple digital communication channels 失效
标题翻译：相对于多个数字通信通道的实时数字信号处理
公开(公告)号：US4991169A
公开(公告)日：1991-02-05
申请号：US227832
申请日：1988-08-02
申请人： Gordon T. Davis , Michael G. Ho Lung , Baiju D. Mandalia , Roland J. Millas , Oscar E. Ortega , Rafael J. Picon , Loran R. Queen , Richard H. Robinson , William R. Robinson, Jr. , Leo A. Sharp, Jr. , Jan W. van den Berg
发明人： Gordon T. Davis , Michael G. Ho Lung , Baiju D. Mandalia , Roland J. Millas , Oscar E. Ortega , Rafael J. Picon , Loran R. Queen , Richard H. Robinson , William R. Robinson, Jr. , Leo A. Sharp, Jr. , Jan W. van den Berg
IPC分类号： H04M11/06 , H04J3/12
CPC分类号： H04J3/12 , H04Q2213/13034 , H04Q2213/1309 , H04Q2213/13103 , H04Q2213/13107 , H04Q2213/13174 , H04Q2213/13199 , H04Q2213/13213 , H04Q2213/13215 , H04Q2213/13292 , H04Q2213/13377 , H04Q2213/13396
摘要： A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.).

28. 发明授权

US4357678A Programmable sequential logic array mechanism 失效
标题翻译：可编程顺序逻辑阵列机制
公开(公告)号：US4357678A
公开(公告)日：1982-11-02
申请号：US106824
申请日：1979-12-26
申请人： Gordon T. Davis
发明人： Gordon T. Davis
IPC分类号： G06F7/00 , G06F9/22 , H03K19/173 , H03K19/177 , H03K19/20
CPC分类号： G06F9/223 , H03K19/1737 , H03K19/17712 , H03K19/1772
摘要： A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.
摘要翻译：提供了一种用于执行逻辑运算和求解逻辑方程的可编程顺序逻辑阵列机制。该机构包括用于接收多个二进制输入信号的搜索阵列子系统。搜索阵列子系统包括用于提供用于测试不同输入信号条件的输入控制字的可寻址存储阵列。顺序逻辑阵列机构还包括用于产生多个二进制输出信号的读阵列子系统。该读取阵列子系统包括用于提供输出信号控制字的可寻址存储阵列。搜索阵列子系统执行的测试结果用于选择哪些输出信号控制字被允许建立或改变读数组输出信号。

29. 发明授权

US07552286B2 Performance of a cache by detecting cache lines that have been reused 有权
标题翻译：通过检测已被重用的高速缓存行来执行缓存的性能
公开(公告)号：US07552286B2
公开(公告)日：2009-06-23
申请号：US12051012
申请日：2008-03-19
申请人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
发明人： Gordon T. Davis , Santiago A. Leon , Hans-Werner Tast
IPC分类号： G06F13/00
CPC分类号： G06F12/127
摘要： A method and system for improving the performance of a cache. The cache may include an array of tag entries where each tag entry includes an additional bit (“reused bit”) used to indicate whether its associated cache line has been reused, i.e., has been requested or referenced by the processor. By tracking whether a cache line has been reused, data (cache line) that may not be reused may be replaced with the new incoming cache line prior to replacing data (cache line) that may be reused. By replacing data in the cache memory that might not be reused prior to replacing data that might be reused, the cache hit may be improved thereby improving performance.
摘要翻译：一种用于提高缓存性能的方法和系统。高速缓存可以包括标签条目的阵列，其中每个标签条目包括用于指示其相关联的高速缓存行是否被重用，即被处理器请求或引用的附加位（“重用位”）。通过跟踪高速缓存行是否被重用，在替换可被重用的数据（高速缓存行）之前，可以用新的传入高速缓存行替换可能不被重用的数据（高速缓存行）。通过在替换可能被重用的数据之前替换高速缓冲存储器中可能不被重用的数据，可以提高高速缓存命中，从而提高性能。

30. 发明申请

US20090158003A1 STRUCTURE FOR A MEMORY-CENTRIC PAGE TABLE WALKER 有权
标题翻译：一个记忆中央页面表格的结构
公开(公告)号：US20090158003A1
公开(公告)日：2009-06-18
申请号：US12109671
申请日：2008-04-25
申请人： Sumedh W. Sathaye , Gordon T. Davis
发明人： Sumedh W. Sathaye , Gordon T. Davis
IPC分类号： G06F9/34
CPC分类号： G06F12/10 , G06F12/0888 , G06F12/1027
摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design is provided. The design structure includes a page table walker. The page table walker is moved from its conventional location in the memory management unit associated with the data processor to a location in main memory i.e. the main memory controller. As a result, wherein the processing of requests for data could selectively avoid or bypass cumbersome caches associated with the data processor.
摘要翻译：提供了一种体现在用于设计，制造和测试设计中的至少一个的机器可读存储介质中的设计结构。设计结构包括页表步行器。页表助行器从与数据处理器相关联的存储器管理单元中的常规位置移动到主存储器（即主存储器控制器）中的位置。结果，其中对数据请求的处理可以选择性地避免或绕过与数据处理器相关联的麻烦的高速缓存。

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