专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06855484B2 Method of depositing low dielectric constant silicon carbide layers 失效
标题翻译：沉积低介电常数碳化硅层的方法
公开(公告)号：US06855484B2
公开(公告)日：2005-02-15
申请号：US10375853
申请日：2003-02-25
申请人： Francimar Campana , Srinivas Nemani , Michael Chapin , Shankar Venkataraman
发明人： Francimar Campana , Srinivas Nemani , Michael Chapin , Shankar Venkataraman
IPC分类号： C23C16/36 , H01L21/027 , H01L21/311 , H01L21/314 , H01L21/768 , C23C16/32
CPC分类号： H01L21/02167 , C23C16/36 , H01L21/02205 , H01L21/02211 , H01L21/02271 , H01L21/0234 , H01L21/0276 , H01L21/31144 , H01L21/314 , H01L21/76808 , H01L21/76813 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L2221/1031
摘要： A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.
摘要翻译：提供一种形成用于集成电路的碳化硅层的方法。碳化硅层通过在电场存在下使包含硅源，碳源和氮源的气体混合物反应而形成。沉积的碳化硅层从氮源中掺入氮。

22. 发明申请

US20080026597A1 METHOD FOR DEPOSITING AND CURING LOW-K FILMS FOR GAPFILL AND CONFORMAL FILM APPLICATIONS 有权
标题翻译：沉积和固化低K膜和胶片应用的方法
公开(公告)号：US20080026597A1
公开(公告)日：2008-01-31
申请号：US11753918
申请日：2007-05-25
申请人： Jeffrey Munro , Srinivas Nemani
发明人： Jeffrey Munro , Srinivas Nemani
IPC分类号： H01L21/31
CPC分类号： H01L21/31633 , C23C16/401 , C23C16/452 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/3105
摘要： Methods of making a silicon oxide layer on a substrate are described. The methods may include forming the silicon oxide layer on the substrate in a reaction chamber by reacting an atomic oxygen precursor and a silicon precursor and depositing reaction products on the substrate. The atomic oxygen precursor is generated outside the reaction chamber. The methods also include heating the silicon oxide layer at a temperature of about 600° C. or less, and exposing the silicon oxide layer to an induced coupled plasma. Additional methods are described where the deposited silicon oxide layer is cured by exposing the layer to ultra-violet light, and also exposing the layer to an induced coupled plasma.
摘要翻译：描述了在衬底上制造氧化硅层的方法。所述方法可以包括通过使原子氧前体和硅前体反应并在基底上沉积反应产物，在反应室中的衬底上形成氧化硅层。原子氧前体在反应室外产生。所述方法还包括在约600℃或更低的温度下加热氧化硅层，并将氧化硅层暴露于感应耦合等离子体。描述了通过将层暴露于紫外光而使沉积的氧化硅层固化并且还将该层暴露于感应耦合等离子体的附加方法。

23. 发明授权

US07176105B2 Dielectric gap fill with oxide selectively deposited over silicon liner 有权
标题翻译：介质间隙填充有选择性沉积在硅衬垫上的氧化物
公开(公告)号：US07176105B2
公开(公告)日：2007-02-13
申请号：US10858135
申请日：2004-06-01
申请人： Srinivas Nemani , Shankar Venkataraman
发明人： Srinivas Nemani , Shankar Venkataraman
IPC分类号： H01L21/336 , H01L21/76 , H01L21/311
CPC分类号： H01L21/76229
摘要： A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner.
摘要翻译：在高纵横比特征中沉积薄层硅以提供用于在其中选择性沉积氧化物的模板。根据一个实施例，在覆盖其中生长的氧化物衬垫的浅沟槽特征中沉积非晶硅。在暴露于溅射之后从沟槽外部去除非晶硅时，氧化物被选择性地沉积在非晶硅之上，以从底部向上填充沟槽而无空隙，从而产生浅沟槽隔离（STI）结构。非晶硅或其它含硅层的沉积允许选择性氧化物沉积步骤与热生长的氧化物沟槽衬里整合。

24. 发明申请

US20060198769A1 Apparatus for abatement of by-products generated from deposition processes and cleaning of deposition chambers 失效
标题翻译：用于减少由沉积工艺产生的副产物和清洁沉积室的装置
公开(公告)号：US20060198769A1
公开(公告)日：2006-09-07
申请号：US11408678
申请日：2006-04-21
申请人： Himanshu Pokharna , Phong Le , Srinivas Nemani
发明人： Himanshu Pokharna , Phong Le , Srinivas Nemani
IPC分类号： B01D50/00 , B01D53/34
CPC分类号： C01B7/191 , B01D53/68 , B01D2251/202 , B01D2257/2027 , C23C16/4405 , C23C16/4412
摘要： Method and apparatus for abating F2 from by-products generated during cleaning of a processing chamber. F2 abatement is efficiently performed by directly injecting H2 in line with a foreline exiting the processing chamber. A tube which is highly resistant to oxidation and corrosive gases, even at high temperature, is connected in line with the foreline as part of the exhaust line of the processing chamber. A cooling jacket may be provided for cooling the tube, since the reaction between F2 and H2 is exothermic. A pressure monitoring arrangement may also be employed to insure that pressure within a hydrogen line, that feeds the injection of H2 into the tube, does not exceed a predetermined pressure value.
摘要翻译：用于在处理室清洁期间产生的副产物减轻F 2的方法和装置。通过直接喷射与排出处理室的前级管线一致的H 2 2来有效地执行F 2 2减排。即使在高温下，耐氧化和腐蚀性气体的管也与作为处理室的排气管线的一部分的前级管线连接。可以提供冷却套管来冷却管，因为F 2和H 2 2之间的反应是放热的。还可以采用压力监测装置来确保将管线内注入H 2 H的氢气管线内的压力不超过预定的压力值。

25. 发明申请

US20060046508A1 SILICON OXIDE GAPFILL DEPOSITION USING LIQUID PRECURSORS 失效
标题翻译：使用液体前驱体的硅氧烷填充沉积物
公开(公告)号：US20060046508A1
公开(公告)日：2006-03-02
申请号：US10931742
申请日：2004-09-01
申请人： Srinivas Nemani , Young Lee
发明人： Srinivas Nemani , Young Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , C23C16/401 , H01L21/02214 , H01L21/02274 , H01L21/0234
摘要： A silicon oxide film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A liquid Si—C—O—H precursor is vaporized. A flow of the vaporized liquid Si—C—O—H precursor is provided to the substrate processing chamber. A gaseous oxidizer is also flowed to the substrate processing chamber. A deposition plasma is generated inductively from the precursor and the oxidizer in the substrate processing chamber, and the silicon oxide film is deposited over the substrate and within the gap with the deposition plasma.
摘要翻译：在设置在基板处理室中的基板上沉积氧化硅膜。基板在相邻的凸起表面之间形成间隙。液体Si-C-O-H前体蒸发。蒸发的液体Si-C-O-H前体的流动被提供到基底处理室。气态氧化剂也流到衬底处理室。从衬底处理室中的前体和氧化剂感应地产生沉积等离子体，并且氧化硅膜沉积在衬底上并且与沉积等离子体在间隙内沉积。

26. 发明申请

US20050266655A1 Dielectric gap fill with oxide selectively deposited over silicon liner 有权
标题翻译：介质间隙填充有选择性沉积在硅衬垫上的氧化物
公开(公告)号：US20050266655A1
公开(公告)日：2005-12-01
申请号：US10858135
申请日：2004-06-01
申请人： Srinivas Nemani , Shankar Venkataraman
发明人： Srinivas Nemani , Shankar Venkataraman
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner.
摘要翻译：在高纵横比特征中沉积薄层硅以提供用于在其中选择性沉积氧化物的模板。根据一个实施例，在覆盖其中生长的氧化物衬垫的浅沟槽特征中沉积非晶硅。在暴露于溅射之后从沟槽外部去除非晶硅时，氧化物被选择性地沉积在非晶硅之上，以从底部向上填充沟槽而无空隙，从而产生浅沟槽隔离（STI）结构。非晶硅或其它含硅层的沉积允许选择性氧化物沉积步骤与热生长的氧化物沟槽衬里整合。

27. 发明申请

US20080057740A1 DOPANT ACTIVATION IN DOPED SEMICONDUCTOR SUBSTRATES 失效
标题翻译：掺杂半导体衬底中的掺杂活性
公开(公告)号：US20080057740A1
公开(公告)日：2008-03-06
申请号：US11844810
申请日：2007-08-24
申请人： Jeffrey Munro , Srinivas Nemani , Young Lee , Marlon Menezes , Christopher Bencher , Vijay Parihar
发明人： Jeffrey Munro , Srinivas Nemani , Young Lee , Marlon Menezes , Christopher Bencher , Vijay Parihar
IPC分类号： H01L21/00
CPC分类号： H01L21/268 , H01L21/26513
摘要： Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500° C. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.
摘要翻译：公开了用于激活掺杂半导体衬底中的掺杂剂的方法。碳前体流入其中设置掺杂半导体衬底的衬底处理室。在基板处理室中由碳前体形成等离子体。用等离子体沉积在衬底上的碳膜。在沉积低于500℃的碳膜的同时保持基板的温度。沉积的碳膜暴露于电磁辐射小于10ms的时间段，并且在电磁波包括的波长处具有大于0.3的消光系数辐射。

28. 发明申请

US20070087522A1 Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner 审中-公开
标题翻译：介质间隙填充选择性沉积在硅衬里上的氧化物
公开(公告)号：US20070087522A1
公开(公告)日：2007-04-19
申请号：US11565726
申请日：2006-12-01
申请人： Srinivas Nemani , Shankar Venkataraman
发明人： Srinivas Nemani , Shankar Venkataraman
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner.
摘要翻译：在高纵横比特征中沉积薄层硅以提供用于在其中选择性沉积氧化物的模板。根据一个实施例，在覆盖其中生长的氧化物衬垫的浅沟槽特征中沉积非晶硅。在暴露于溅射之后从沟槽外部去除非晶硅时，氧化物被选择性地沉积在非晶硅之上，以从底部向上填充沟槽而无空隙，从而产生浅沟槽隔离（STI）结构。非晶硅或其它含硅层的沉积允许选择性氧化物沉积步骤与热生长的氧化物沟槽衬里整合。

29. 发明授权

US07200460B2 Method of depositing low dielectric constant silicon carbide layers 有权
标题翻译：沉积低介电常数碳化硅层的方法
公开(公告)号：US07200460B2
公开(公告)日：2007-04-03
申请号：US10375793
申请日：2003-02-25
申请人： Francimar Campana , Srinivas Nemani , Michael Chapin , Shankar Venkataraman
发明人： Francimar Campana , Srinivas Nemani , Michael Chapin , Shankar Venkataraman
IPC分类号： G06F19/00 , C23C16/00 , G03C5/00
CPC分类号： H01L21/02167 , C23C16/36 , H01L21/02205 , H01L21/02211 , H01L21/02271 , H01L21/0234 , H01L21/0276 , H01L21/31144 , H01L21/314 , H01L21/76808 , H01L21/76813 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L2221/1031
摘要： A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.
摘要翻译：提供一种形成用于集成电路的碳化硅层的方法。碳化硅层通过在电场存在下使包含硅源，碳源和氮源的气体混合物反应而形成。沉积的碳化硅层从氮源中掺入氮。

30. 发明申请

US20070054504A1 Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 失效
标题翻译：后沉积等离子体处理以增加HDP-CVD SIO2的拉伸应力
公开(公告)号：US20070054504A1
公开(公告)日：2007-03-08
申请号：US11221303
申请日：2005-09-07
申请人： Xiaolin Chen , Srinivas Nemani , DongQing Li , Jeffrey Munro , Marlon Menezes
发明人： Xiaolin Chen , Srinivas Nemani , DongQing Li , Jeffrey Munro , Marlon Menezes
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , C23C16/402 , C23C16/56 , H01L21/02164 , H01L21/02274 , H01L21/0234 , H01L21/31612
摘要： A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.
摘要翻译：描述了用于增加硅晶片的拉伸应力的等离子体处理工艺。在基底上沉积介电层之后，将衬底提升到衬底接收表面上方的升高位置，并暴露于等离子体处理工艺，其处理晶片的顶表面和底表面并增加沉积层的拉伸应力。本发明的另一实施例涉及在等离子体处理之前偏压衬底以用等离子体离子轰击晶片并提高衬底的温度。在本发明的另一个实施例中，可以使用两步等离子体处理工艺，其中首先在沉积后直接在处理位置处暴露于等离子体，然后升高到晶片的顶部和底部两者的升高位置暴露于等离子体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式