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    • 21. 发明授权
    • Network interface with host independent buffer management
    • 具有主机独立缓存管理的网络接口
    • US5299313A
    • 1994-03-29
    • US921519
    • 1992-07-28
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • Brian PetersenW. Paul ShererDavid R. BrownLai-Chin Lo
    • G06F13/00G06F13/12H04L13/08
    • G06F13/128
    • A network interface controller controls communication between a host system and a network transceiver coupled to a network comprises a memory outside of the host address space in which receive and transmit buffers are managed, host interface logic emulating memory mapped registers in the host address space, for transferring data between the host address space and the buffer memory, and network interface logic coupled with the network transceiver, for transferring data between the buffers in the buffer memory and the network transceiver. The buffer memory includes a transmit descriptor ring buffer, transmit data buffer, transfer descriptor buffer, and receive ring buffer all managed by operations transparent to the host.
    • 网络接口控制器控制主机系统和耦合到网络的网络收发器之间的通信,包括主机地址空间外的存储器,其中管理接收和发送缓冲器的主机接口逻辑,模拟主机地址空间中的存储器映射寄存器,用于 在主机地址空间和缓冲存储器之间传送数据,以及与网络收发器耦合的网络接口逻辑,用于在缓冲存储器中的缓冲器和网络收发器之间传送数据。 缓冲存储器包括发送描述符环形缓冲器,发送数据缓冲器,传输描述符缓冲器和接收环形缓冲器,全部由对主机透明的操作管理。
    • 24. 发明授权
    • Network switching system having variable headers and addresses
    • 具有变量头和地址的网络交换系统
    • US08553684B2
    • 2013-10-08
    • US11643540
    • 2006-12-21
    • Brian Petersen
    • Brian Petersen
    • H04L12/28
    • H04L49/15H04L49/25H04L49/3009H04L49/3045H04L49/3072H04L49/50
    • According to an example embodiment, a method may include receiving a message, appending a header set to the message, and transmitting the message from an ingress port to an egress port of the network switching system based on the header set. In an example embodiment, the header set may include a variable number of headers, wherein one or more of the headers in the header set includes a next header field to identify a type of header following a current header in the header set. In an example embodiment, the packet may be segmented and transmitted across the switching system as a plurality of cells, where a cell destination address may be a portion (e.g., subset of bits) of the packet destination address.
    • 根据示例实施例,一种方法可以包括:接收消息,将报头集合附加到所述消息,以及基于所述报头集合将所述消息从入口端口传送到所述网络交换系统的出口端口。 在一个示例实施例中,报头集合可以包括可变数目的报头,其中报头集合中的一个或多个报头包括下一个报头字段,用于标识报头集合中的当前报头之后的报头类型。 在示例实施例中,分组可以被分段并且作为多个小区跨越交换系统发送,其中小区目的地地址可以是分组目的地地址的一部分(例如,比特的子集)。
    • 25. 发明申请
    • Network switching system having variable headers and addresses
    • 具有变量头和地址的网络交换系统
    • US20070248086A1
    • 2007-10-25
    • US11643540
    • 2006-12-21
    • Brian Petersen
    • Brian Petersen
    • H04L12/56
    • H04L49/15H04L49/25H04L49/3009H04L49/3045H04L49/3072H04L49/50
    • According to an example embodiment, a method may include receiving a message, appending a header set to the message, and transmitting the message from an ingress port to an egress port of the network switching system based on the header set. In an example embodiment, the header set may include a variable number of headers, wherein one or more of the headers in the header set includes a next header field to identify a type of header following a current header in the header set. In an example embodiment, the packet may be segmented and transmitted across the switching system as a plurality of cells, where a cell destination address may be a portion (e.g., subset of bits) of the packet destination address.
    • 根据示例实施例,一种方法可以包括:接收消息,将报头集合附加到所述消息,以及基于所述报头集合将所述消息从入口端口传送到所述网络交换系统的出口端口。 在一个示例实施例中,报头集合可以包括可变数目的报头,其中报头集合中的一个或多个报头包括下一个报头字段,用于标识报头集合中的当前报头之后的报头类型。 在示例实施例中,分组可以被分段并且作为多个小区跨越交换系统发送,其中小区目的地地址可以是分组目的地地址的一部分(例如,比特的子集)。
    • 28. 发明授权
    • Reduced pin-count 10Base-T MAC to transceiver interface
    • 引脚数10Base-T MAC到收发器接口
    • US06631138B1
    • 2003-10-07
    • US09339637
    • 1999-06-24
    • Stewart FindlaterJames R. RiversDavid H. YenBrian PetersenBernard N. DainesDavid Talaski
    • Stewart FindlaterJames R. RiversDavid H. YenBrian PetersenBernard N. DainesDavid Talaski
    • H04J317
    • H04L7/0008H04J3/0697
    • Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of nine times the number of ports, and the addition of each additional port requires only two more wires (pins).
    • 提供了一个10Base-T MAC到PHY接口,每个端口只需要两根电线(引脚),另外两根全球线:时钟线(引脚)和同步线(引脚)。 通过时分复用实现与每个端口相关联的引脚数目的减少,其中每个时分复用引线组合来自常规七线接口的多个定义。 因此,每个端口都有自己的一对相关联的时分复用电线(引脚),并且每个端口的添加只需要两根额外的电线。 根据本发明的优选实施例,在10MHz的常规七线接口中通常在九条线路上传输的信息被时分复用到以40MHz传输数据的两条线(对应于两个引脚)四倍 常规接口的速度。 重要的是,这种复用是以端口为基础完成的。 因此,MAC到收发器接口所需的引脚数量是端口数量的两倍,而不是端口数量的九倍,而每个附加端口的添加只需要两个电线(引脚)。
    • 29. 发明授权
    • Network adapter with an indication signal mask and an interrupt signal
mask
    • 具有指示信号掩码和中断信号掩码的网络适配器
    • US5530874A
    • 1996-06-25
    • US012561
    • 1993-02-02
    • Scott A. EmeryBrian PetersenW. Paul Sherer
    • Scott A. EmeryBrian PetersenW. Paul Sherer
    • G06F13/00G06F13/24G06F9/46
    • G06F13/24
    • Indication and interrupt signals generated by a network adapter representing asynchronous events are managed by a host system. The network adapter includes a first mask logic for selectively disabling the indication signals from being stored in a first memory location by the host writing to a first mask register. A second mask logic which is coupled to the first memory location also selectively disables the indication signals from being stored in a second memory location creating two levels of status information. The indication signals may also be disabled from being stored in the second memory location responsive to the host writing to a second mask register. The first memory location may be read from the host in order to determine whether a network event occurred during an interrupt service routine, while interrupt means generates an interrupt signal to the host responsive to the value in the second memory location. A third level of control is provided by an internal counter which allows for automatic enabling and/or disabling of a plurality of indications and interrupts with and without explicit commands in the host driver subroutines.
    • 由代表异步事件的网络适配器产生的指示和中断信号由主机系统管理。 网络适​​配器包括第一屏蔽逻辑,用于通过主机向第一屏蔽寄存器写入来选择性地禁用指示信号存储在第一存储器位置。 耦合到第一存储器位置的第二掩模逻辑还选择性地禁止指示信号被存储在创建两级状态信息的第二存储器位置中。 响应于主机向第二屏蔽寄存器的写入,也可以禁止指示信号存储在第二存储单元中。 可以从主机读取第一存储器位置,以便确定在中断服务程序期间是否发生网络事件,而中断装置响应于第二存储器位置中的值产生对主机的中断信号。 第三级控制由内部计数器提供,其允许在主机驱动程序子程序中使用和不使用显式命令来自动启用和/或禁用多个指示和中断。
    • 30. 发明授权
    • Recursive packet header processing
    • 递归包头处理
    • US08284776B2
    • 2012-10-09
    • US12609769
    • 2009-10-30
    • Brian Petersen
    • Brian Petersen
    • H04L12/28H04L12/56H04J3/16H04J3/24
    • H04L45/00H04L45/742H04L69/22
    • According to one general aspect, an apparatus may include an ingress port, a header cache, and a plurality of ingress recursion engines. In some embodiments, the ingress port may be configured to receive a packet that comprises a data portion and a header portion, wherein the header portion comprises at least one header. In various embodiments, the header cache may be configured to store at least a part of the header portion of the packet. In one embodiment, the plurality of ingress recursion engines may be configured to recursively process the header portion, from outer-most header to inner-most header, until an adjacency value for the packet is determined. In some embodiments, each ingress recursion engine may be configured to process a header from the header portion.
    • 根据一个一般方面,装置可以包括入口端口,报头缓存和多个入口递归引擎。 在一些实施例中,入口端口可以被配置为接收包括数据部分和报头部分的分组,其中报头部分包括至少一个报头。 在各种实施例中,报头高速缓存可以被配置为存储分组的报头部分的至少一部分。 在一个实施例中,多个入口递归引擎可以被配置为递归地处理从最外层报头到最内层报头的报头部分,直到确定该分组的邻接值。 在一些实施例中,每个入口递归引擎可以被配置为从头部部分处理头部。