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21. 发明授权

US06321003B1 Tunable semiconductor laser system 有权
标题翻译：可调谐半导体激光系统
公开(公告)号：US06321003B1
公开(公告)日：2001-11-20
申请号：US09686129
申请日：2000-10-10
申请人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： G02B628
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A multiplexer for a wavelength division multiplexed optical communication system includes an optical circulator with at least first, second, third and fourth circulator ports. An optical fiber with a first optical transmission path is coupled to the first circulator port and carries a wavelength division multiplexed optical signal that includes signals 1−n. A second optical transmission path is in optical communication with the second circulator port. A first laser is coupled to the second optical transmission path. The first laser reflects the 1−n signals and adds a signal n+1. A control loop is coupled to the first laser. In response to a detected change in temperature the control loop sends a signal to adjust a voltage or current supplied to the first laser and provide a controlled frequency and power of an output beam. A third optical transmission path is in optical communication with the third circulator port and transmits the signals 1−n and the signals n+1 that are received from the optical circulator. A fourth optical transmission path is in optical communication with the fourth optical circulator port. The fourth optical transmission path is positioned after the second optical transmission path and before the third optical transmission path. A first optoelectronic device is coupled to the fourth optical transmission path.
摘要翻译：用于波分复用光通信系统的多路复用器包括具有至少第一，第二，第三和第四循环端口的光循环器。具有第一光传输路径的光纤耦合到第一循环端口，并携带包括信号1-n的波分复用光信号。第二光传输路径与第二环行器端口光通信。第一激光器耦合到第二光传输路径。第一激光器反射1-n个信号并加上信号n + 1。控制回路耦合到第一激光器。响应于检测到的温度变化，控制回路发送信号以调节提供给第一激光器的电压或电流，并提供输出光束的受控频率和功率。第三光传输路径与第三环行器端口光通信，并发送从光环行器接收的信号1-n和信号n + 1。第四光传输路径与第四光循环器端口光通信。第四光传输路径位于第二光传输路径之后且位于第三光传输路径之前。第一光电子器件耦合到第四光传输路径。

22. 发明授权

US5652533A Circuit for generating sampling signals at closely spaced time intervals 失效
标题翻译：用于以紧密间隔的时间间隔产生采样信号的电路
公开(公告)号：US5652533A
公开(公告)日：1997-07-29
申请号：US545560
申请日：1995-10-19
申请人： Hee Wong , Gabriel Li
发明人： Hee Wong , Gabriel Li
IPC分类号： H03K5/15 , H03K5/22
CPC分类号： H03K5/15073
摘要： An electronic circuit suitable for sampling an incoming data bit stream in order to recover the information contained in the data stream contains an input section, a reference section, and a comparing section. The input section produces a ramp signal that switches between a first endpoint voltage and a second endpoint voltage in a periodic manner. The reference section furnishes a plurality of reference voltages between the two endpoint voltages. The comparing section compares the ramp signal to the reference voltages to produce corresponding sampling signals. Each sampling signal makes a first voltage transition as the ramp signal passes a corresponding reference voltage in going from the second endpoint voltage to the first endpoint voltage. Accordingly, the first transitions of the sampling signals occur in groups, each group being spread out in time during part of a period of the ramp signal. A data sampling portion of the circuit utilizes the sampling signals to sample the input data bit stream.
摘要翻译：适于对进入的数据比特流进行采样以便恢复包含在数据流中的信息的电子电路包含输入部分，参考部分和比较部分。输入部分产生以周期性方式在第一端点电压和第二端点电压之间切换的斜坡信号。参考部分在两个端点电压之间提供多个参考电压。比较部分将斜坡信号与参考电压进行比较，以产生相应的采样信号。当斜坡信号从第二端点电压进入第一端点电压时，每个采样信号进行第一电压转换。因此，采样信号的第一跃迁以组为单位发生，每个组在斜坡信号的一段时间的一部分期间在时间上展开。电路的数据采样部分利用采样信号对输入数据位流进行采样。

23. 发明授权

US08218598B1 Method to program the starting phase of the spread spectrum 有权
标题翻译：编程扩频开始阶段的方法
公开(公告)号：US08218598B1
公开(公告)日：2012-07-10
申请号：US12054328
申请日：2008-03-24
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04B1/00
CPC分类号： H04B15/04
摘要： Disclosed is a circuit and method to program the starting phase of the spread spectrum of a clock output. The circuit includes a plurality of phase locked loop (PLL) circuits for generating a plurality of spread spectrum waveforms. The circuit also includes a spread control circuit for controlling each of the plurality of PLL circuits in accordance with a plurality of respective spread profiles. The spread profiles are configured to vary a starting phase of each spread spectrum waveform such that a total energy of each spread spectrum waveform is out of phase with other spread spectrum waveforms.
摘要翻译：公开了一种用于对时钟输出的扩展频谱的起始阶段进行编程的电路和方法。该电路包括用于产生多个扩展频谱波形的多个锁相环（PLL）电路。电路还包括扩展控制电路，用于根据多个相应的扩展分布来控制多个PLL电路中的每一个。扩展分布被配置为改变每个扩频波形的起始相位，使得每个扩展频谱波形的总能量与其他扩展频谱波形异相。

24. 发明申请

US20110252162A1 MEMORY SYSTEM AND METHOD 有权
标题翻译：记忆系统和方法
公开(公告)号：US20110252162A1
公开(公告)日：2011-10-13
申请号：US12819794
申请日：2010-06-21
申请人： Jun Li , Gabriel Li
发明人： Jun Li , Gabriel Li
IPC分类号： G06F13/42 , G06F13/14
CPC分类号： G06F13/28 , G06F13/1684
摘要： In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.
摘要翻译：在一个实施例中，一种装置包括存储器控制器，其被配置为控制通过菊花链式总线连接的多个菊花链连接的存储器组件。菊花链式总线包括从存储器控制器的发送接口到初始存储器组件的接收接口的直接连接以及从初始存储器组件的发送接口到下一个存储器组件的接收接口的菊花链连接。总线从最后存储器组件的发送接口直接延伸到存储器控制器的接收接口。

25. 发明授权

US07219252B1 Apparatus and method for dynamic overclocking 有权
标题翻译：动态超频的设备和方法
公开(公告)号：US07219252B1
公开(公告)日：2007-05-15
申请号：US10888470
申请日：2004-07-09
申请人： Gabriel Li , Chwei-Po Chew , Johnson Tsai
发明人： Gabriel Li , Chwei-Po Chew , Johnson Tsai
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： According to embodiments of the invention, temperature, current, or other physical quantities associated with an integrated circuit, which can also include a processor, may be converted to a digital signal, and that digital signal used to choose a corresponding frequency offset that is added to any pre-established overclocking frequency. Embodiments of the invention allow a user to specify a dynamic range between which the frequency offset is bounded during overclocking of the integrated circuit. The programmable lower limit specifies the frequency where the integrated circuit begins to overclock. The programmable upper limit specifies the maximum overclocking frequency that is allowed. Setting the lower limit to be equal to the upper limit forces overclocking to occur at only the specified value.
摘要翻译：根据本发明的实施例，与集成电路相关联的温度，电流或其他物理量（其也可以包括处理器）可以被转换为数字信号，并且该数字信号用于选择相应的频率偏移量到任何预先建立的超频频率。本发明的实施例允许用户在集成电路的超频期间指定频率偏移界定的动态范围。可编程下限指定集成电路开始超频的频率。可编程上限指定允许的最大超频频率。将下限设置为等于上限强制超频仅在指定值发生。

26. 发明申请

US20070053475A1 Circuit, System, and Method for Multiplexing Signals with Reduced Jitter 有权
标题翻译：具有减少抖动的多路复用信号的电路，系统和方法
公开(公告)号：US20070053475A1
公开(公告)日：2007-03-08
申请号：US11468195
申请日：2006-08-29
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.
摘要翻译：本文提供了一种多路复用器电路，系统和方法，用于通过消除多路复用器电路内的所有串扰和电源噪声注入来复用具有减小的抖动的信号。例如，可以通过以下步骤来消除串扰和电源噪声注入：（i）将多路复用功能分离成三个单独的逻辑门，并且（ii）每个逻辑门仅允许一个开关输入。在某些情况下，可以通过在三个不同的电源域分配逻辑门来进一步降低抖动。换句话说，逻辑门输入可以通过门控其自身功率域中的每个信号来进一步隔离。此外，多路复用器电路通过利用三个基本相同的逻辑门来提供内置的延迟匹配。

27. 发明授权

US06553503B1 Circuitry, architecture and method(s) for synchronizing data 有权
公开(公告)号：US06553503B1
公开(公告)日：2003-04-22
申请号：US09391865
申请日：1999-09-08
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： G06F104
CPC分类号： H04J3/0626 , G06F5/14 , H04L7/04 , H04L25/14
摘要： An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.

28. 发明授权

US06351476B2 Tunable semiconductor laser system 有权
标题翻译：可调谐半导体激光系统
公开(公告)号：US06351476B2
公开(公告)日：2002-02-26
申请号：US09761542
申请日：2001-01-16
申请人： Peter Kner , Gabriel Li , D. Philip Worland , Rang-Chen Yu , Wupen Yuen
发明人： Peter Kner , Gabriel Li , D. Philip Worland , Rang-Chen Yu , Wupen Yuen
IPC分类号： H01S310
CPC分类号： H01S5/06804 , H01L2224/48091 , H01L2924/16195 , H01S5/0078 , H01S5/02248 , H01S5/0687 , H01S5/18366 , H01L2924/00014
摘要： A tunable semiconductor laser system includes a laser with a semiconductor active region positioned between upper and lower confining regions of opposite type semiconductor material. First and second reflective members are positioned at opposing edges of the active and confining regions. A wavelength tuning member and a temperature sensor are coupled to the laser. A control loop is coupled to the temperature sensor and the tuning member. In response to a detected change in temperature the control loop sends an adjustment signal to the tuning member and the tuning member adjusts a voltage or current supplied to the laser to provide a controlled output beam of selected wavelength.
摘要翻译：可调谐半导体激光器系统包括具有半导体有源区域的激光器，该半导体有源区域位于相对的半导体材料的上部和下部约束区域之间。第一和第二反射构件定位在活动和限制区域的相对边缘处。波长调谐构件和温度传感器耦合到激光器。控制回路耦合到温度传感器和调谐构件。响应于检测到的温度变化，控制回路向调谐构件发送调整信号，并且调谐构件调节提供给激光器的电压或电流以提供所选波长的受控输出光束。

29. 发明授权

US5651036A Third harmonic suppression scheme for a wave used in a phase-to-frequency converter 失效
标题翻译：用于在相变频器中使用的波的三次谐波抑制方案
公开(公告)号：US5651036A
公开(公告)日：1997-07-22
申请号：US644036
申请日：1996-05-09
申请人： Wong Hee , Gabriel Li
发明人： Wong Hee , Gabriel Li
IPC分类号： H03L7/099 , H04L7/00
CPC分类号： H03L7/099
摘要： A phase-to-frequency converter uses a triangular waveform synthesizer to generate a triangular wave using both PDM and a DC modulation scheme. A 4-bit PDM and associated logic generates the PDM output waveform with polarity information and two switching waveforms that encode the DC level information to provide a resultant sum. The resulting waveform, after filtering, is the multiple phases of the triangular waveform. The generated multiple phases of the triangular wave are then modified by reducing the ramp rate at appropriate points to suppress the third harmonic and its multiples. The ramp rate is proportional to the pulse density output of the Pulse Density Modulator. In one embodiment, the rate of the PDM output is reduced by one half during appropriate periods by gating the output by its clock, thereby reducing its density by one half during those periods.
摘要翻译：相位到频率转换器使用三角波形合成器来使用PDM和DC调制方案来产生三角波。 4位PDM和相关逻辑产生具有极性信息的PDM输出波形和用于编码直流电平信息以提供结果和的两个开关波形。滤波后的结果波形是三角波形的多个相位。然后通过在适当的点减小斜坡率来抑制三次谐波及其倍数，从而修改产生的三角波的多相。斜坡率与脉冲密度调制器的脉冲密度输出成比例。在一个实施例中，PDM输出的速率在合适的时间期间通过将输出选通其时钟来减小一半，从而在这些周期期间将其密度降低一半。

30. 发明授权

US08373455B1 Output buffer circuit 有权
标题翻译：输出缓冲电路
公开(公告)号：US08373455B1
公开(公告)日：2013-02-12
申请号：US13013725
申请日：2011-01-25
申请人： Alan McLaughlin , Gabriel Li
发明人： Alan McLaughlin , Gabriel Li
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K19/018521
摘要： An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.
摘要翻译：输出驱动器电路可以包括至少第一驱动器晶体管，其具有耦合在第一电源节点和输出节点之间的源极 - 漏极路径。第一可变电流源可以产生具有与电源电压成反比的至少一个分量的电流。第一驱动器开关元件可以与至少第一驱动器晶体管的栅极和第二电源节点之间的第一可变电流源串联耦合。

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