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21. 发明授权

US08302040B2 Compact model methodology for PC landing pad lithographic rounding impact on device performance 有权
标题翻译： PC着陆垫光刻圆形的紧凑型模型方法对设备性能的影响
公开(公告)号：US08302040B2
公开(公告)日：2012-10-30
申请号：US13100584
申请日：2011-05-04
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.
摘要翻译：一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。

22. 发明授权

US07979815B2 Compact model methodology for PC landing pad lithographic rounding impact on device performance 有权
标题翻译： PC着陆垫光刻圆形的紧凑型模型方法对设备性能的影响
公开(公告)号：US07979815B2
公开(公告)日：2011-07-12
申请号：US11970990
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.
摘要翻译：一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。

23. 发明授权

US07928571B2 Device having dual etch stop liner and reformed silicide layer and related methods 有权
标题翻译：具有双蚀刻停止衬垫和重整硅化物层的器件及相关方法
公开(公告)号：US07928571B2
公开(公告)日：2011-04-19
申请号：US11850968
申请日：2007-09-06
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L27/088 , H01L29/40 , H01L23/48 , H01L23/52 , H01L23/62
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

24. 发明授权

US07446062B2 Device having dual etch stop liner and reformed silicide layer and related methods 有权
标题翻译：具有双蚀刻停止衬垫和重整硅化物层的器件及相关方法
公开(公告)号：US07446062B2
公开(公告)日：2008-11-04
申请号：US10905027
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L21/318 , H01L21/44
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

25. 发明申请

US20080108228A1 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 有权
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：US20080108228A1
公开(公告)日：2008-05-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/31
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

26. 发明授权

US07306983B2 Method for forming dual etch stop liner and protective layer in a semiconductor device 有权
标题翻译：在半导体器件中形成双蚀刻停止衬垫和保护层的方法
公开(公告)号：US07306983B2
公开(公告)日：2007-12-11
申请号：US10905024
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/3185 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.
摘要翻译：本发明提供一种半导体器件，其具有双氮化物衬垫，硅化物层和位于氮化物衬底之下的保护层，用于防止蚀刻硅化物层。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：向器件施加保护层，向器件施加第一氮化硅衬垫，去除第一氮化硅衬垫的一部分，去除所述保护层的一部分，以及向所述装置施加第二氮化硅衬垫。

27. 发明申请

US20110225562A1 COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE 有权
标题翻译：用于PC路面平台的简化模型方法对设备性能的影响
公开(公告)号：US20110225562A1
公开(公告)日：2011-09-15
申请号：US13100584
申请日：2011-05-04
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F9/455
CPC分类号： G06F17/5036
摘要： A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature.
摘要翻译：一种用于对具有有源器件区域，栅极结构并且包括连接到栅极结构并且设置在有源器件区域上方的导线特征来建模半导体晶体管器件结构的方法和计算机程序产品，所述导电线特征包括导电层衬垫特征设置在待建模的电路中的有源器件区域的边缘附近。该方法包括确定由着陆焊盘特征限定的边缘与有源器件区域的边缘之间的距离，以及通过建模着陆焊盘特征的光刻圆整效应，确定作为功能的有源器件区域的宽度变化由着陆垫特征限定的边缘到活动设备区域的边缘之间的距离。根据这些数据，有源器件区域宽度（deltaW加法器）的有效变化与确定的距离有关。然后，晶体管紧凑型模型中的晶体管模型参数值被更新为晶体管器件，以包括要添加到内置deltaW值的ΔW加法器值。在设备仿真中使用的网表可以包括deltaW加法器值，以量化着陆垫特征的光刻舍入效应的影响。

28. 发明授权

US07348635B2 Device having enhanced stress state and related methods 有权
标题翻译：具有增强的应力状态和相关方法的装置
公开(公告)号：US07348635B2
公开(公告)日：2008-03-25
申请号：US10905025
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L31/00
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

29. 发明申请

US20060128145A1 DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS 有权
标题翻译：具有双层蚀刻层和改性硅酸盐层的装置及相关方法
公开(公告)号：US20060128145A1
公开(公告)日：2006-06-15
申请号：US10905027
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L21/44 , H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层的厚度和电阻基本上类似于未暴露于形成双重氮化硅衬里的硅化物层。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

30. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

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