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21. 发明申请

US20120309172A1 Epitaxial Lift-Off and Wafer Reuse 审中-公开
标题翻译：外延提升和晶圆再利用
公开(公告)号：US20120309172A1
公开(公告)日：2012-12-06
申请号：US13118900
申请日：2011-05-31
申请人： Linda T. Romano , David P. Bour , Richard J. Brown , Andrew P. Edwards , Isik C. Kizilyalli , Hui Nie , Thomas R. Prunty
发明人： Linda T. Romano , David P. Bour , Richard J. Brown , Andrew P. Edwards , Isik C. Kizilyalli , Hui Nie , Thomas R. Prunty
IPC分类号： H01L21/20
CPC分类号： H01L21/2654 , H01L21/02002 , H01L21/02389 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/02664 , H01L33/0079
摘要： A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.
摘要翻译：根据本发明的实施例的重新使用III族氮化物生长衬底的方法包括在III族氮化物衬底上外延生长III族氮化物半导体结构。 III族氮化物半导体结构包括在牺牲层上生长的牺牲层和附加层。牺牲层植入至少一种植入物种。在注入的牺牲层处将III族氮化物衬底与附加层分离。在一些实施例中，III族氮化物衬底是GaN，牺牲层是GaN，含铝的III族氮化物层或含铟的III族氮化物层。在一些实施例中，通过蚀刻注入的牺牲层将III族氮化物衬底与附加层分离。

22. 发明授权

US5977612A Semiconductor devices constructed from crystallites 失效
标题翻译：由微晶构成的半导体器件
公开(公告)号：US5977612A
公开(公告)日：1999-11-02
申请号：US770403
申请日：1996-12-20
申请人： David P. Bour , Fernando A. Ponce , G. A. Neville Connell , Ross D. Bringans , Noble M. Johnson , Werner K. Goetz , Linda T. Romano
发明人： David P. Bour , Fernando A. Ponce , G. A. Neville Connell , Ross D. Bringans , Noble M. Johnson , Werner K. Goetz , Linda T. Romano
IPC分类号： H01S5/00 , H01L29/201 , H01L33/16 , H01L33/32 , H01S5/323 , H01S5/343 , H01L29/06
CPC分类号： H01L33/32 , B82Y20/00 , H01L29/201 , H01L33/16 , H01S5/34333
摘要： The present invention relates to electronic devices formed in crystallites of III-V nitride materials. Specifically, the present invention simplifies the processing technology required for the fabrication of high-performance electronic devices in III-V nitride materials.
摘要翻译：本发明涉及以III-V族氮化物材料微晶形成的电子器件。具体地说，本发明简化了在III-V族氮化物材料中制造高性能电子器件所需的加工技术。

23. 发明授权

US06163557A Fabrication of group III-V nitrides on mesas 失效
标题翻译：在台面上制备III-V族氮化物
公开(公告)号：US06163557A
公开(公告)日：2000-12-19
申请号：US82154
申请日：1998-05-21
申请人： Clarence J. Dunnrowicz , Linda T. Romano , David P. Bour
发明人： Clarence J. Dunnrowicz , Linda T. Romano , David P. Bour
IPC分类号： C30B25/02 , H01L21/20 , H01L33/00 , H01S5/02 , H01S5/323 , H01L31/0312 , H01S5/00
CPC分类号： C30B25/02 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L33/007 , H01S5/0207 , H01S5/0213 , H01S5/0217 , H01S5/3202 , H01S5/32341
摘要： Group III-V nitride films are fabricated on mesas patterned either on substrates such as sapphire substrates, or on mesas patterned on group III-V nitride layers grown on substrates. The mesas provide reduced area surfaces for epitaxially growing group III-V nitride films, to reduce thermal film stresses in the films to reduce cracking. The surfaces of the mesas on which the films are grown are dimensioned and oriented to reduce the number of thin film crack planes that can grow on the mesas. Further cracking reduction in the films can be achieved by thinning the substrate to form membranes. The reduced substrate thickness at the membranes reduces the thermal expansion mismatch tensile stress in the films. The mesas can reduce or eliminate the occurrence of cracks in GaN or AlGaN epitaxial films grown on the mesas, for percentages of aluminum in the AlGaN films of up to about 18%. The improved group III-V nitride films can be used in optoelectronic devices including LEDs and edge and surface emitting laser diodes.
摘要翻译： III-V族氮化物薄膜制造在图案化的基板上，例如蓝宝石衬底上，或者在生长在衬底上的III-V族氮化物层上图案化的台面上。台面为外延生长的III-V族氮化物薄膜提供减少的面积表面，以减少薄膜中的热薄膜应力以减少开裂。其上生长膜的台面的表面的尺寸和尺寸被定向以减少可以在台面上生长的薄膜裂纹平面的数量。膜的进一步裂解减少可以通过使基材变薄以形成膜来实现。在薄膜处降低的基底厚度降低了薄膜中的热膨胀失配拉伸应力。台面可以减少或消除在台面上生长的GaN或AlGaN外延膜中的裂纹的发生，AlGaN膜中铝的百分比高达约18％。改进的III-V族III族氮化物薄膜可用于包括LED和边缘和表面发射激光二极管在内的光电器件。

24. 发明授权

US07951693B2 III-nitride light emitting devices grown on templates to reduce strain 有权
标题翻译：在模板上生长的III族氮化物发光器件以减少应变
公开(公告)号：US07951693B2
公开(公告)日：2011-05-31
申请号：US11615808
申请日：2006-12-22
申请人： Patrick N. Grillot , Nathan F. Gardner , Werner K. Goetz , Linda T. Romano
发明人： Patrick N. Grillot , Nathan F. Gardner , Werner K. Goetz , Linda T. Romano
IPC分类号： H01L21/20
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/02505 , H01L21/0254 , H01L21/0262
摘要： In a III-nitride light emitting device, the device layers including the light emitting layer are grown over a template designed to reduce strain in the device, in particular in the light emitting layer. Reducing the strain in the light emitting device may improve the performance of the device. The template may expand the lattice constant in the light emitting layer over the range of lattice constants available from conventional growth templates. Strain is defined as follows: a given layer has a bulk lattice constant abulk corresponding to a lattice constant of a free standing material of a same composition as that layer and an in-plane lattice constant ain-plane corresponding to a lattice constant of that layer as grown in the structure. The amount of strain in a layer is |(ain-plane−abulk)|/abulk. In some embodiments, the strain in the light emitting layer is less than 1%.
摘要翻译：在III族氮化物发光器件中，包括发光层的器件层在设计成减小器件中特别是在发光层中的应变的模板上生长。降低发光器件中的应变可以提高器件的性能。模板可以在常规生长模板可获得的晶格常数的范围内扩展发光层中的晶格常数。应变定义如下：给定层具有对应于与该层相同组成的自由材料的晶格常数的块状晶格常数吸收和对应于该层的晶格常数的面内晶格常数ain-平面如在结构中生长。一层中的应变量为|（ain-plane-abulk）| / abulk。在一些实施方案中，发光层中的应变小于1％。

25. 发明授权

US07932511B2 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
标题翻译：大面积纳米大电子基板及其用途
公开(公告)号：US07932511B2
公开(公告)日：2011-04-26
申请号：US11681058
申请日：2007-03-01
申请人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Wallace Parce , Jay L. Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence Bock , David Stumbo , J. Wallace Parce , Jay L. Goldman
IPC分类号： H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
摘要翻译：描述了具有多个半导体器件的电子基片的方法和装置。在衬底上形成纳米线薄膜。纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。在纳米线的薄膜中限定多个半导体区域。在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

26. 发明申请

US20100167512A1 Methods for Nanostructure Doping 审中-公开
标题翻译：纳米结构掺杂方法
公开(公告)号：US20100167512A1
公开(公告)日：2010-07-01
申请号：US12720125
申请日：2010-03-09
申请人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
发明人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
IPC分类号： H01L21/22
CPC分类号： H01L29/0665 , B81C1/00698 , B81C2201/0173 , B82Y10/00 , H01L21/2256 , H01L21/268 , H01L29/0673
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.
摘要翻译：公开了掺杂纳米结构的方法，例如纳米线。该方法提供了改进现有掺杂纳米结构方法的各种方法。这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

27. 发明授权

US07701014B2 Gating configurations and improved contacts in nanowire-based electronic devices 失效
标题翻译：基于纳米线的电子设备的选通配置和改进的接触
公开(公告)号：US07701014B2
公开(公告)日：2010-04-20
申请号：US12244573
申请日：2008-10-02
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L27/088
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

28. 发明授权

US07560366B1 Nanowire horizontal growth and substrate removal 有权
标题翻译：纳米线水平生长和底物去除
公开(公告)号：US07560366B1
公开(公告)日：2009-07-14
申请号：US11291484
申请日：2005-12-01
申请人： Linda T. Romano , Shahriar Mostarshed
发明人： Linda T. Romano , Shahriar Mostarshed
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02532 , C30B11/12 , C30B29/06 , C30B29/60 , H01L21/02573 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02645 , Y10S977/742 , Y10S977/743 , Y10S977/762
摘要： The present invention provides processes for producing horizontal nanowires that are separate and oriented and allow for processing directly on a substrate material. The nanowires grow horizontally by suppressing vertical growth from a nucleating particle, such as a metal film. The present invention also provides for horizontal nanowire growth from nucleating particles on the edges of nanometer-sized steps. Following processing, the nanowires can be removed from the substrate and transferred to other substrates. The present invention also provides for nanowires produced by these processes and electronic devices comprising these nanowires. The present invention also provides for nanowire growth apparatus that provide horizontal nanowires, and processes for producing nanowire devices.
摘要翻译：本发明提供了用于生产分离和取向的水平纳米线的方法，并允许直接在基底材料上加工。纳米线通过抑制诸如金属膜的成核颗粒的垂直生长而水平生长。本发明还提供了纳米尺寸步骤边缘上的成核颗粒的水平纳米线生长。在处理之后，可以将纳米线从基底上移除并转移到其它基底。本发明还提供了由这些方法生产的纳米线和包括这些纳米线的电子器件。本发明还提供了提供水平纳米线的纳米线生长装置和用于制备纳米线装置的方法。

29. 发明授权

US07427328B2 Large-area nanoenabled macroelectronic substrates and uses therefor 有权
标题翻译：大面积纳米大电子基板及其用途
公开(公告)号：US07427328B2
公开(公告)日：2008-09-23
申请号：US11602783
申请日：2006-11-21
申请人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence A. Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
发明人： Xiangfeng Duan , Chunming Niu , Stephen A. Empedocles , Linda T. Romano , Jian Chen , Vijendra Sahi , Lawrence A. Bock , David P. Stumbo , J. Wallace Parce , Jay L. Goldman
IPC分类号： B05C5/00 , B05B7/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01F1/405 , H01L27/092 , H01L27/12 , H01L27/1292 , H01L29/0673 , H01L29/068 , H01L29/78696 , H01L31/035281 , H01L33/18 , H01L33/20 , H01L33/24 , H01L51/0048 , H01L51/0504 , H01L51/0545 , H01L51/0595 , Y10S977/742 , Y10S977/762 , Y10S977/781 , Y10S977/789 , Y10S977/938
摘要： A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.
摘要翻译：描述了具有多个半导体器件的电子基片的方法和装置。在衬底上形成纳米线薄膜。纳米线的薄膜形成为具有足够的纳米线密度以达到工作电流水平。在纳米线的薄膜中限定多个半导体区域。在半导体器件区域处形成触点，从而提供与多个半导体器件的电连接。此外，用于制造纳米线的各种材料，包括p掺杂纳米线和n掺杂纳米线的薄膜，纳米线异质结构，发光纳米线异质结构，用于在衬底上定位纳米线的流动掩模，用于沉积纳米线的纳米线喷涂技术，用于减少或消除声子的技术描述了纳米线中的电子散射，以及用于降低纳米线中的表面状态的技术。

30. 发明授权

US07422980B1 Methods of positioning and/or orienting nanostructures 有权
标题翻译：定位和/或定向纳米结构的方法
公开(公告)号：US07422980B1
公开(公告)日：2008-09-09
申请号：US11602784
申请日：2006-11-21
申请人： Xiangfeng Duan , R. Hugh Daniels , Chunming Niu , Vijendra Sahi , James M. Hamilton , Linda T. Romano
发明人： Xiangfeng Duan , R. Hugh Daniels , Chunming Niu , Vijendra Sahi , James M. Hamilton , Linda T. Romano
IPC分类号： H01L21/44 , H01L21/441
CPC分类号： H01L51/0048 , B01J23/52 , B81B2203/0361 , B81B2207/015 , B81C3/005 , B81C99/008 , B81C2203/057 , B82B3/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G11B5/743 , G11C2213/81 , H01L29/7869 , H01L51/0001 , H01L51/0595 , H01L2924/0002 , Y10S438/962 , Y10S977/762 , Y10S977/856 , Y10S977/857 , Y10S977/858 , Y10S977/89 , H01L2924/00
摘要： Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.
摘要翻译：在表面上定位和取向纳米结构，特别是纳米线的方法用于随后的使用或整合。该方法单独使用基于掩模的工艺，或者与纳米结构的基于流动的对准组合以在表面上提供定向和定位的纳米结构。还提供了定位和/或定向的纳米结构的群体，包括定位和/或定向纳米结构的群体，用于定位和/或取向纳米结构的系统以及相关设备，系统和方法。

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