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21. 发明授权

US06801986B2 Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation 失效
标题翻译：在加载锁定/存储条件原子存储器操作期间，通过延迟所有权所有权投降来实现预防行为
公开(公告)号：US06801986B2
公开(公告)日：2004-10-05
申请号：US09933536
申请日：2001-08-20
申请人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
发明人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834
摘要： A method, for executing a load locked and a store conditional instruction in a processor, achieves an atomic read-write operation to a memory block. First the load locked instruction is executed to read a memory block, and the processor in response to executing the load locked instruction issues a read modify system command to read the block and to take ownership of the block by the processor, and also sets a lock flag for the address of the memory block, and writes a value of the memory block into a cache of the processor as a cache copy of the memory block. The lock flag, upon receipt of an invalidate message by the processor for the cache copy of the memory block, is reset if any invalidate messages for the memory block are received by the processor. The processor waits for a selected time interval before the processor surrenders ownership of the memory block upon receipt of an ownership request message, if any is received by the processor after execution of the load locked instruction. The processor executes the store conditional instruction, and the processor in response to executing the store conditional instruction tests the lock flag, and if the lock flag is set, writing to the cache copy of the memory block. The processor ends, in the event that the lock flag is reset, the store conditional instruction and does not write to the cache copy of the memory block.
摘要翻译：一种用于在处理器中执行加载锁定和存储条件指令的方法，对存储器块实现原子读写操作。首先执行加载锁定指令以读取存储器块，并且响应于执行加载锁定指令的处理器发出读取修改系统命令来读取块并由处理器获取块的所有权，并且还设置锁定标记存储器块的地址，并将存储器块的值写入处理器的高速缓存作为存储器块的高速缓存副本。如果处理器接收到存储块的任何无效消息，则锁定标志在由处理器接收到存储器块的高速缓存副本的无效消息时被重置。处理器在接收到所有权请求消息之后处理器递交所述存储器块的所有权，等待处理器选定的时间间隔（如果在执行加载锁定指令之后由处理器接收到）。处理器执行存储条件指令，并且处理器响应于执行存储条件指令测试锁定标志，并且如果设置了锁定标志，则写入存储器块的高速缓存副本。处理器在锁定标志被复位的情况下结束，存储条件指令，并且不写入存储器块的高速缓存副本。

22. 发明授权

US06209065B1 Mechanism for optimizing generation of commit-signals in a distributed shared-memory system 失效
标题翻译：优化分布式共享内存系统中提交信号生成的机制
公开(公告)号：US06209065B1
公开(公告)日：2001-03-27
申请号：US08957230
申请日：1997-10-24
申请人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
发明人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
IPC分类号： G06F1314
CPC分类号： G06F9/542 , G06F9/52
摘要： A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The mechanism generally comprises a structure that indicates whether the memory reference operation affects other processors of other nodes of the multiprocessor system. An ordering point of the local node generates an optimized commit-signal when the structure indicates that the memory reference operation does not affect the other processors.
摘要翻译：一种机制响应于处理器向具有用于互连多个节点的分层交换机的多处理器系统的本地节点发出的存储器参考操作来优化多处理器系统的控制逻辑的生成提交信号。该机制通常包括指示存储器参考操作是否影响多处理器系统的其他节点的其他处理器的结构。当结构指示存储器参考操作不影响其他处理器时，本地节点的排序点生成优化的提交信号。

23. 发明授权

US6088771A Mechanism for reducing latency of memory barrier operations on a multiprocessor system 失效
标题翻译：减少多处理器系统上存储器屏障操作延迟的机制
公开(公告)号：US6088771A
公开(公告)日：2000-07-11
申请号：US957501
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Kourosh Gharachorloo , Stephen R. Van Doren
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Kourosh Gharachorloo , Stephen R. Van Doren
IPC分类号： G06F9/45 , G06F13/00
CPC分类号： G06F9/3004 , G06F8/458 , G06F9/30087 , G06F9/3834
摘要： A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately after issuing a first set of memory reference operations (i.e., the pre-MB operations) without waiting for responses to those pre-MB operations. Issuance of the MB operation to the system results in serialization of that operation and generation of a MB Acknowledgment (MB-Ack) command. The MB-Ack is loaded into a probe queue of the issuing processor and, according to the invention, functions to pull-in all previously ordered invalidate and probe commands in that queue. By ensuring that the probes and invalidates are ordered before the MB-Ack is received at the issuing processor, the inventive technique provides the appearance that all pre-MB references have completed.
摘要翻译：一种技术减少了用于在处理器向具有共享存储器的多处理器系统发出的存储器参考操作的集合之间施加参考间顺序的存储器屏障（MB）操作的等待时间。该技术包括在发出第一组存储器参考操作（即，预MB操作）之前立即发出MB操作，而不等待对那些MB前操作的响应。向系统发出MB操作会导致该操作的序列化和生成MB确认（MB-Ack）命令。 MB-Ack被加载到发布处理器的探测队列中，并且根据本发明，该功能用于在该队列中引入所有先前订购的无效和探测命令。通过确保在发布处理器接收到MB-Ack之前对探测和无效进行排序，本发明技术提供了所有pre-MB引用完成的外观。

24. 发明授权

US6055605A Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches 失效
标题翻译：用于在具有共享高速缓存的多处理器系统中使用提交信号来减少参考间排序的等待时间的技术
公开(公告)号：US6055605A
公开(公告)日：2000-04-25
申请号：US957544
申请日：1997-10-24
申请人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
发明人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00 , G06F12/00
CPC分类号： G06F12/084
摘要： A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.
摘要翻译：一种技术减少了具有分配在共享高速缓存的多个处理器之间的共享存储器的多处理器系统中的存储器参考操作组之间的参考间排序的等待时间。根据该技术，共享高速缓存的每个处理器响应由共享该高速缓存的另一个处理器发出的存储器引用操作而继承由多处理器系统的控制逻辑产生的提交信号。提交信号通过指示对系统的那些实体的存储器参考操作的明显完成来促进多处理器系统的处理器和共享存储器实体之间的串行化。

25. 发明授权

US08176259B2 System and method for resolving transactions in a cache coherency protocol 有权
标题翻译：用于解决高速缓存一致性协议中的事务的系统和方法
公开(公告)号：US08176259B2
公开(公告)日：2012-05-08
申请号：US10760813
申请日：2004-01-20
申请人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
发明人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
IPC分类号： G06F13/38
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0828
摘要： A system comprises a first node that employs a source broadcast protocol to initiate a transaction. The first node employs a forward progress protocol to resolve the transaction if the source broadcast protocol cannot provide a deterministic resolution of the transaction.
摘要翻译：系统包括采用源广播协议来发起事务的第一节点。如果源广播协议不能提供事务的确定性分辨率，则第一节点采用前进进程协议来解决事务。

26. 发明授权

US07395374B2 System and method for conflict responses in a cache coherency protocol with ordering point migration 有权
标题翻译：具有排序点迁移的缓存一致性协议中的冲突响应的系统和方法
公开(公告)号：US07395374B2
公开(公告)日：2008-07-01
申请号：US10760651
申请日：2004-01-20
申请人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Gregory Edward Tierney , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Systems and methods are disclosed for interaction between different cache coherency protocols. One system may comprise a home node that receives a request for data from a first node in a first cache coherency protocol. A second node provides a conflict response to a request for the data from the home node. The conflict response indicates that an ordering point for the data is migrating according to a second cache coherency protocol, which is different from the first cache coherency protocol.
摘要翻译：公开了用于不同高速缓存一致性协议之间的交互的系统和方法。一个系统可以包括家庭节点，其在第一高速缓存一致性协议中从第一节点接收对数据的请求。第二节点向来自家节点的数据的请求提供冲突响应。冲突响应指示数据的排序点根据与第一高速缓存一致性协议不同的第二高速缓存一致性协议进行迁移。

27. 发明授权

US07376794B2 Coherent signal in a multi-processor system 失效
标题翻译：多处理器系统中的相干信号
公开(公告)号：US07376794B2
公开(公告)日：2008-05-20
申请号：US10756636
申请日：2004-01-13
申请人： Simon C. Steely, Jr. , Gregory Edward Tierney , Stephen R. Van Doren
发明人： Simon C. Steely, Jr. , Gregory Edward Tierney , Stephen R. Van Doren
IPC分类号： G06F9/00 , G06F9/38 , G06F13/00
CPC分类号： G06F12/0822
摘要： Multi-processor systems and methods are disclosed. One embodiment may comprise a multi-processor system comprising at least one data fill provided to a source processor in response to a source request by the source processor, and a coherent signal generated by the multi-processor system that provides an indication of which data fill of the at least one data fill is a coherent data fill.
摘要翻译：公开了多处理器系统和方法。一个实施例可以包括多处理器系统，其包括响应于源处理器的源请求而提供给源处理器的至少一个数据填充，以及由多处理器系统生成的相干信号，其提供哪个数据填充的指示所述至少一个数据填充是相干数据填充。

28. 发明授权

US07177987B2 System and method for responses between different cache coherency protocols 有权
标题翻译：用于不同缓存一致性协议之间的响应的系统和方法
公开(公告)号：US07177987B2
公开(公告)日：2007-02-13
申请号：US10760436
申请日：2004-01-20
申请人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
发明人： Stephen R. Van Doren , Gregory Edward Tierney , Simon C. Steely, Jr.
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0828 , G06F2212/2542
摘要： Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
摘要翻译：公开了用于为不同的高速缓存一致性协议提供响应的系统和方法。一个实施例可以包括包括采用第一高速缓存一致性协议的第一节点的系统。与第一节点相关联的检测器基于由第一节点向根据第二高速缓存一致性协议提供的请求提供的响应来检测条件，第二高速缓存一致性协议不同于第一高速缓存一致性协议。第一节点提供对根据检测器检测到的条件而变化的对第一节点的给定一个请求的响应。

29. 发明授权

US07174431B2 Mechanism for resolving ambiguous invalidates in a computer system 有权
标题翻译：在计算机系统中解决模糊无效的机制
公开(公告)号：US07174431B2
公开(公告)日：2007-02-06
申请号：US11258586
申请日：2005-10-25
申请人： Stephen R. Van Doren , Gregory E. Tierney
发明人： Stephen R. Van Doren , Gregory E. Tierney
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0808
摘要： The invention provides a system and method for resolving ambiguous invalidate messages received by an entity of a computer system. An invalidate message is considered ambiguous when the receiving entity cannot tell whether it applies to a previously victimized memory block or to a memory block that the entity is waiting to receive. When an entity receives such an invalidate message, it stores the message in its miss address file (MAF). When the entity subsequently receives the memory block, the entity “replays” the Invalidate message from its MAF by invalidating the block from its cache and issuing an Acknowledgement (Ack) to the entity that triggered issuance of the Invalidate message command.
摘要翻译：本发明提供了一种用于解决由计算机系统的实体接收的模糊无效消息的系统和方法。当接收实体不能判断它是否适用于先前受到伤害的存储器块或实体正在等待接收的存储器块时，无效消息被认为是模糊的。当实体接收到这样的无效消息时，它将消息存储在其未命中的地址文件（MAF）中。当实体随后接收到该存储器块时，该实体通过使该块从其高速缓存失效并向触发发出无效消息命令的实体发出一个确认（Ack），从其MAF“重播”无效消息。

30. 发明授权

US07024520B2 System and method enabling efficient cache line reuse in a computer system 有权
标题翻译：在计算机系统中实现高效缓存行重用的系统和方法
公开(公告)号：US07024520B2
公开(公告)日：2006-04-04
申请号：US10263740
申请日：2002-10-03
申请人： Gregory E. Tierney , Stephen R. Van Doren
发明人： Gregory E. Tierney , Stephen R. Van Doren
IPC分类号： G06F12/00
CPC分类号： G06F12/0822 , G06F12/0804
摘要： A system permits unacknowledged write backs in a computer. The computer has a plurality of processors and a shared memory. The shared memory stores data in terms of memory blocks, and each processor has a cache. Associated with each cache line is a tag containing the address of the block at that line, and its state. A duplicate copy of the tag information (DTAG) for each processor cache is also provided, and each section of the DTAG that corresponds to a given processor is organized into a primary DTAG region and a secondary DTAG region. The secondary DTAG region preferably stores tag information for a dirty version of a block, while the write back of the block is in flight to memory. This frees the primary DTAG region to store tag information for a block other than the dirty block, but using the same cache line.
摘要翻译：系统在计算机中允许未确认的回写。计算机具有多个处理器和共享存储器。共享存储器根据存储器块存储数据，并且每个处理器具有高速缓存。与每个高速缓存行相关联的是一个标签，其中包含该行的块的地址及其状态。还提供了每个处理器高速缓存的标签信息（DTAG）的重复副本，并且对应于给定处理器的DTAG的每个部分被组织成主DTAG区域和辅助DTAG区域。次级DTAG区域优选地存储块的脏版本的标签信息，同时块的回写正在飞行到存储器。这将释放主DTAG区域以存储除脏块之外的块的标签信息，但使用相同的高速缓存行。

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