专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07082480B2 Managing bus transaction dependencies 失效
标题翻译：管理总线事务依赖关系
公开(公告)号：US07082480B2
公开(公告)日：2006-07-25
申请号：US10674944
申请日：2003-09-29
申请人： Zohar Bogin , Serafin E. Garcia
发明人： Zohar Bogin , Serafin E. Garcia
IPC分类号： G06F3/00
CPC分类号： G06F13/24 , G06F13/385
摘要： A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
摘要翻译：在具有调度器和多个下行命令队列的计算机系统中防止死锁和活动锁的技术的组合。在一个实施例中，需要在所有受影响的下游命令队列中同时可用空间的广播事务变成延迟的事务，使得命令队列被保留，并且重试其他事务直到广播事务完成。在另一个实施例中，如果事务在预定时间内未完成，则使用拯救计时器推迟事务。在另一个实施例中，如果存在小于可用于该事务的预定量的下游缓冲区空间，则潜在地解决由可编程属性映射控制的存储空间的锁定事务被处理为延迟事务。

22. 发明授权

US06983339B1 Method and apparatus for processing interrupts of a bus 失效
标题翻译：一种用于处理总线中断的方法和装置
公开(公告)号：US06983339B1
公开(公告)日：2006-01-03
申请号：US09675801
申请日：2000-09-29
申请人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
发明人： Jeffrey L. Rabe , Satish Acharya , Zohar Bogin , Serafin E. Garcia , David J. Harriman
IPC分类号： G06F1/00
CPC分类号： G06F13/24
摘要： A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.
摘要翻译：一种用于将APIC中断传送到处理器和处理器之间的方法和装置，作为FSB事务。由PCI设备生成的中断和硬件信号被转换为上游存储器写入中断，并进一步转换为由处理器接收的FSB中断事务。标记为最低优先级可重定向的中断根据任务优先级信息重定向。提供对XTPR事务的支持以更新XTPR寄存器。提供XTPR更新事务和重定向中断的优先顺序。

23. 发明申请

US20050143843A1 Command pacing 审中-公开
标题翻译：命令起搏
公开(公告)号：US20050143843A1
公开(公告)日：2005-06-30
申请号：US10723132
申请日：2003-11-25
申请人： Zohar Bogin , Arthur Hunter , Krishnamurthy Venkataramana , Mihir Shah
发明人： Zohar Bogin , Arthur Hunter , Krishnamurthy Venkataramana , Mihir Shah
IPC分类号： G05B11/01 , G10L19/14
CPC分类号： G10L19/167
摘要： Machine-readable media, methods, and apparatus are described to pace commands to codecs. Some embodiments comprise an audio controller that transfers frames to codecs and places commands in the frames at a pace dictated by a command pacer.
摘要翻译：描述了机器可读介质，方法和装置，以将命令调整到编解码器。一些实施例包括音频控制器，该音频控制器将帧传送到编解码器，并以由命令起搏器指示的速度将命令放置在帧中。

24. 发明申请

US20050114569A1 Tracking progress of data streamer 有权
标题翻译：跟踪数据流的进度
公开(公告)号：US20050114569A1
公开(公告)日：2005-05-26
申请号：US10723347
申请日：2003-11-25
申请人： Zohar Bogin , Brent Chartrand , Arthur Hunter
发明人： Zohar Bogin , Brent Chartrand , Arthur Hunter
IPC分类号： G06F13/16 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： Machine-readable media, methods, and apparatus are described to stream data between a codec and a buffer in system memory and to maintain a value in system memory that is indicative of a current position in the buffer. In some embodiments, an audio controller streams the data across an isochronous channel having relaxed ordering rules to the buffer in the system memory and updates the value indicative of current position via a write across the isochronous channel to the system memory.
摘要翻译：描述了机器可读介质，方法和装置，以在系统存储器中的编解码器和缓冲器之间流式传输数据，并维持指示缓冲器中当前位置的系统存储器中的值。在一些实施例中，音频控制器通过具有放松排序规则的同步信道将数据流传输到系统存储器中的缓冲器，并且通过跨同步信道的写入更新指示当前位置的值到系统存储器。

25. 发明授权

US06502150B1 Method and apparatus for resource sharing in a multi-processor system 失效
标题翻译：多处理器系统资源共享的方法和装置
公开(公告)号：US06502150B1
公开(公告)日：2002-12-31
申请号：US09205649
申请日：1998-12-03
申请人： Zohar Bogin , Narendra S. Khandekar , Steve J. Clohset
发明人： Zohar Bogin , Narendra S. Khandekar , Steve J. Clohset
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.
摘要翻译：提供了包括至少两个主机代理的计算机系统。计算机系统还包括芯片组，其包括要由至少两个主机代理共享的资源。芯片组耦合到至少两个主机代理。芯片组防止占用共享资源的第一主机代理访问共享资源，直到第二个主机代理在访问所述共享资源时取得进展。

26. 发明授权

US5533200A Method and apparatus for transmission of signals over a shared line 失效
标题翻译：用于在共享线路上传输信号的方法和装置
公开(公告)号：US5533200A
公开(公告)日：1996-07-02
申请号：US210560
申请日：1994-03-18
申请人： Timothy M. Dobbins , Zohar Bogin
发明人： Timothy M. Dobbins , Zohar Bogin
IPC分类号： G06F13/36 , G06F1/22 , G06F13/00 , G06F13/364
CPC分类号： G06F13/364 , G06F1/22
摘要： A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.
摘要翻译：半导体部件能够控制计算机系统中的多个半导体部件之间的信息传输。半导体部件包括能够通过共享线路发送第一类型的信号的第一信号发生器和能够在线路上发送第二类型的信号的第二信号发生器。它还包括能够控制第一信号发生器的第一逻辑器件和能够控制第二信号发生器的第二逻辑器件。

27. 发明授权

US09100693B2 Methods and apparatuses for securing playback content 有权
标题翻译：保护播放内容的方法和装置
公开(公告)号：US09100693B2
公开(公告)日：2015-08-04
申请号：US12796502
申请日：2010-06-08
申请人： Balaji Vembu , Suryaprasad Kareenahalli , Daniel Nemiroff , Zohar Bogin , Raul Gutierrez
发明人： Balaji Vembu , Suryaprasad Kareenahalli , Daniel Nemiroff , Zohar Bogin , Raul Gutierrez
IPC分类号： H04L29/06 , H04N21/4405 , H04N21/426 , H04N21/4408 , G06F21/10
CPC分类号： H04N21/4405 , G06F21/10 , H04N21/4181 , H04N21/42623 , H04N21/4408
摘要： An apparatus for secured playback is presented. In one embodiment, the apparatus includes a controller that includes a key derivation module to manage authentication and key derivation. In one embodiment, the apparatus provides a video decryption key to a graphics engine if video data portions in a data stream are retrievable without having to decrypt the data stream. In one embodiment, the apparatus also includes a decryption module to decrypt a part of data in conjunction with an encryption key to generate video information and video data. The controller then writes an encrypted version of the video data to a video buffer of a graphics engine.
摘要翻译：提出了一种用于安全播放的设备。在一个实施例中，该装置包括控制器，其包括用于管理认证和密钥推导的密钥导出模块。在一个实施例中，如果可以检索数据流中的视频数据部分而不必对数据流进行解密，则该装置向图形引擎提供视频解密密钥。在一个实施例中，该装置还包括解密模块，用于结合加密密钥对一部分数据进行解密以产生视频信息和视频数据。然后，控制器将视频数据的加密版本写入图形引擎的视频缓冲器。

28. 发明申请

US20100169883A1 PROVIDING MULTIPLE VIRTUAL DEVICE CONTROLLERS BY REDIRECTING AN INTERRUPT FROM A PHYSICAL DEVICE CONTROLLER 有权
标题翻译：通过重定向物理设备控制器的中断来提供多个虚拟设备控制器
公开(公告)号：US20100169883A1
公开(公告)日：2010-07-01
申请号：US12347970
申请日：2008-12-31
申请人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
发明人： Zohar Bogin , Suryaprasad Kareenahaili , Rajeev K. Nalawadi , Michael Tabet , Darren Abramson
IPC分类号： G06F9/455
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/45558 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.
摘要翻译：公开了通过从物理设备控制器重定向中断来提供多个虚拟设备控制器的设备，方法和系统的实施例。在一个实施例中，装置包括处理器，物理设备控制器和虚拟化逻辑。虚拟化逻辑是从物理设备控制器接收第一中断，并且作为响应，从多个虚拟设备控制器之一向处理器发送第二中断。

29. 发明申请

US20070239955A1 Memory Scoreboard 失效
标题翻译：记忆记分板
公开(公告)号：US20070239955A1
公开(公告)日：2007-10-11
申请号：US11394462
申请日：2006-03-30
申请人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
发明人： Chee Teh , Suryaprasad Kareenahalli , Zohar Bogin
IPC分类号： G06F13/28
CPC分类号： G06F13/1668 , G06F12/0215
摘要： Embodiments of a memory scoreboard are presented herein.
摘要翻译：记忆记分板的实施例在本文中给出。

30. 发明授权

US06915407B2 Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller 有权
标题翻译：用于存储器控制器中的主机系统总线的低延迟源同步地址接收器的方法和装置
公开(公告)号：US06915407B2
公开(公告)日：2005-07-05
申请号：US10813145
申请日：2004-03-30
申请人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
发明人： Srinivasan T. Rajappa , Romesh B. Trivedi , Rajagopal Subramanian , Zohar Bogin , Serafin Garcia
IPC分类号： G06F13/40 , G06F12/00
CPC分类号： G06F13/4054
摘要： A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.
摘要翻译：一种用于系统总线的源同步地址接收器的方法和装置。在一个实施例中，输入到存储器总线的系统总线地址之间的流通由两个输入来控制：一个是源同步地址选通，指示接收器锁存地址并存储数据，而另一个是协议信号，表示地址转移的开始。流通电路响应于数字地址选通信号和数字地址选择信号产生使能信号，以在接收到地址分组之前生成具有地址分组和使能的流通门的使能信号信号作为输入。数字地址数据包出现在地址引脚上时，流通门将数字地址数据包（交易地址）的第一个分量提供给芯片组。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式