专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20130171829A1 Titanium-Nitride Removal 有权
标题翻译：去除钛 - 氮化物
公开(公告)号：US20130171829A1
公开(公告)日：2013-07-04
申请号：US13343190
申请日：2012-01-04
申请人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
发明人： John A. Fitzsimmons , Shyng-Tsong Chen , David L. Rath , Muthumanickam Sankarapandian , Oscar van der Straten
IPC分类号： H01L21/3065 , C11D7/60
CPC分类号： C09K13/00 , H01L21/02063 , H01L21/31144 , H01L21/32134 , H01L21/76802 , H01L21/76804
摘要： A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.
摘要翻译：一种去除不需要的金属硬掩模的化学溶液，但仍然对器件布线冶金和电介质材料具有选择性。本发明通过在接收结构金属化之前选择性去除金属硬掩模而不损害限定半导体器件所需的任何现有金属或介电材料，从而降低纵横比，例如，铜冶金或器件电介质。因此，将导致金属填充物的改进的纵横比，而不会对设备的限定的金属接收结构引入任何过大的梯形横截面特征。

22. 发明授权

US08337627B2 Cleaning exhaust screens in a manufacturing process 有权
标题翻译：在制造过程中清洁排气筛
公开(公告)号：US08337627B2
公开(公告)日：2012-12-25
申请号：US12571477
申请日：2009-10-01
申请人： John A. Fitzsimmons , Richard O. Henry
发明人： John A. Fitzsimmons , Richard O. Henry
IPC分类号： B08B3/08 , B01D41/04 , B01D29/66
CPC分类号： B08B3/08 , B01D41/04
摘要： A method of cleaning an screen in a manufacturing process step that employs a chamber including a drain line having a screen configured and disposed in the chamber above the drain line to trap soluble materials includes detecting a build-up of soluble material on the screen, ceasing a work operation in the chamber, and initiating a screen cleaning operation. The screen cleaning operation includes closing a computer operated valve fluidly connected to the drain line to fluidly isolate a portion of the chamber, automatically introducing an amount of solvent into the chamber once the computer operated valve is closed with the amount of solvent filling the chamber and/or the drain line to fully immerse the screen, and opening the operated valve after a predetermined amount of time to empty the chamber and the drain line of solvent once the soluble materials trapped on the screen are dissolved.
摘要翻译：一种在制造工艺步骤中清洁屏幕的方法，该方法采用包括排水线的室，该室具有配置并设置在排出管线上方的室内的筛网以捕获可溶性材料，包括检测可溶物质在筛网上的积聚，停止在室中进行工作操作，并启动屏幕清洁操作。屏幕清洁操作包括关闭流体地连接到排水管线的计算机操作的阀，以流体地隔离室的一部分，一旦计算机操作的阀被填充室的溶剂量封闭，则自动将一定量的溶剂引入室中， /或排水管线，以完全浸没屏幕，并且一旦被捕获在屏幕上的可溶性材料溶解，则在预定量的时间之后打开操作的阀以清空溶剂和溶剂的排出管线。

23. 发明授权

US08294270B2 Copper alloy via bottom liner 失效
标题翻译：铜合金通过底衬
公开(公告)号：US08294270B2
公开(公告)日：2012-10-23
申请号：US13116622
申请日：2011-05-26
申请人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
发明人： Daniel C. Edelstein , Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Anthony K. Stamper
IPC分类号： H01L23/52
CPC分类号： H01L23/53238 , H01L23/5226 , H01L2924/0002 , Y10T428/12493 , H01L2924/00
摘要： Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.
摘要翻译：通过在集成电路中的铜通孔/布线连接中形成铜合金，同时通过将合金限制在所述合金的界面区域来最小化合金的不利电效应来获得铜集成电路互连的改进的机械和粘合强度和断裂性通孔/布线连接，而不在其他地方，通过减小或基本消除导电路径中合金的厚度。通过所有可用的合金材料与铜，铜合金或其他金属及其合金的反应，合金位置和组成进一步稳定。

24. 发明授权

US08236610B2 Forming semiconductor chip connections 有权
标题翻译：形成半导体芯片连接
公开(公告)号：US08236610B2
公开(公告)日：2012-08-07
申请号：US12471656
申请日：2009-05-26
申请人： Louis Lu-Chen Hsu , Kangguo Cheng , Timothy J. Dalton , Mukta G. Farooq , John A. Fitzsimmons
发明人： Louis Lu-Chen Hsu , Kangguo Cheng , Timothy J. Dalton , Mukta G. Farooq , John A. Fitzsimmons
IPC分类号： H01L21/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/14 , H01L21/6836 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L27/0207 , H01L29/0657 , H01L2224/0401 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/06183 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/14183 , H01L2224/16 , H01L2224/16105 , H01L2224/16137 , H01L2224/16147 , H01L2224/81205 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06551 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
摘要翻译：公开了能够形成半导体芯片连接的系统和方法。在一个实施例中，半导体芯片包括具有一对相对侧面的多面体形状的主体; 以及沿着在多面体形状的一对相对侧之间延伸的一侧延伸的焊料构件。

25. 发明申请

US20110111590A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20110111590A1
公开(公告)日：2011-05-12
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译：一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻特征跨越到多个互连的侧壁。

26. 发明授权

US07755206B2 Pad structure to provide improved stress relief 有权
标题翻译：垫结构提供改善的应力消除
公开(公告)号：US07755206B2
公开(公告)日：2010-07-13
申请号：US11947184
申请日：2007-11-29
申请人： Mukta G. Farooq , John A. Fitzsimmons , Thomas J. Fleischman
发明人： Mukta G. Farooq , John A. Fitzsimmons , Thomas J. Fleischman
IPC分类号： H01L23/48
CPC分类号： B81B3/0072 , B81B2207/07 , H01L24/72 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/00
摘要： A semiconductor interconnection comprises a semiconductor device, a substrate adjacent the semiconductor device, and a plurality of spring contacts on the semiconductor device or the substrate. A plurality of solder connections are on the opposite semiconductor device or substrate. Each spring contact comprises a contact surface and a conductive material on the contact surface. Upon assembly of the semiconductor device and the substrate, the conductive material on the plurality of spring contacts makes contact with each of the plurality of solder connections. The conductive material is in a liquid state at manufacturing or operating temperatures of the semiconductor device. Thus, the conductive material could be a solid at room temperature and transition to a liquid state at the semiconductor's manufacturing or operating temperatures.
摘要翻译：半导体互连包括半导体器件，与半导体器件相邻的衬底，以及半导体器件或衬底上的多个弹簧触点。多个焊接连接在相对的半导体器件或衬底上。每个弹簧触点包括在接触表面上的接触表面和导电材料。在组装半导体器件和衬底时，多个弹簧触头上的导电材料与多个焊料连接中的每一个接触。导电材料在半导体器件的制造或工作温度下处于液态。因此，导电材料在室温下可以是固体，并且在半导体的制造或操作温度下转变为液态。

27. 发明授权

US07592685B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US07592685B2
公开(公告)日：2009-09-22
申请号：US11849048
申请日：2007-08-31
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L29/93
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.
摘要翻译：半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个间隙，跨越多于互连的最小间隔。

28. 发明授权

US07566649B2 Compressible films surrounding solder connectors 有权
标题翻译：围绕焊料连接器的可压缩薄膜
公开(公告)号：US07566649B2
公开(公告)日：2009-07-28
申请号：US11858147
申请日：2007-09-20
申请人： William E. Bernier , Tien-Jen Cheng , Marie S. Cole , David E. Eichstadt , Mukta G. Farooq , John A. Fitzsimmons , Lewis S. Goldmann , John U. Knickerbocker , Tasha E. Lopez , David J. Welsh
发明人： William E. Bernier , Tien-Jen Cheng , Marie S. Cole , David E. Eichstadt , Mukta G. Farooq , John A. Fitzsimmons , Lewis S. Goldmann , John U. Knickerbocker , Tasha E. Lopez , David J. Welsh
IPC分类号： H01L21/44 , H01L21/50 , H01L21/48 , H01L23/52 , H01L23/48 , H01L23/485 , H01L23/488
CPC分类号： H01L21/563 , H01L23/3171 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/10126 , H01L2224/13099 , H01L2224/131 , H01L2224/13566 , H01L2224/16 , H01L2224/73203 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01R43/0256 , H05K3/284 , H05K3/3436 , H05K2201/0133 , H05K2201/10977 , Y02P70/613 , H01L2224/29099 , H01L2224/0401
摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.
摘要翻译：公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上），并用绝缘底部填充物填充载体和装置之间的间隙。

29. 发明授权

US07405147B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US07405147B2
公开(公告)日：2008-07-29
申请号：US10707996
申请日：2004-01-30
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lines or vias.
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线或通孔上或附近形成间隙。

30. 发明授权

US06960519B1 Interconnect structure improvements 失效
标题翻译：互连结构改进
公开(公告)号：US06960519B1
公开(公告)日：2005-11-01
申请号：US10710210
申请日：2004-06-25
申请人： Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Lee M. Nicholson , Andrew H. Simon , Anthony K. Stamper
发明人： Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Lee M. Nicholson , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/44 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76877 , H01L21/76804 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods and conductive interconnect structures are provided for preventing cracks in a dielectric layer on a substrate. Substantially half cylindrical or cylindrical trench openings are formed within at least one dielectric layer, which are then filled with a high conductivity metal for forming substantially half cylindrical or cylindrical wires. The rounded bottom portions of the substantially half cylindrical wires, or the rounded bottom and top portions of the substantially half cylindrical wires, avoid any propagation points for starting cracks in the dielectric layer, as compared to conventional rectangular conductors having angled edges, which in fact are propagation points for initiating cracks. The substantially half cylindrical or cylindrical wires also reduce the line-to-line capacitance between neighboring wires, substantially eliminate any high stress points in the dielectric layer, reduce mechanical stresses induced on the IC and increase the overall mechanical strength of the IC.
摘要翻译：提供了方法和导电互连结构，用于防止基板上的电介质层中的裂纹。在至少一个电介质层内形成基本上半圆柱形的或圆柱形的沟槽开口，然后用一个高导电性金属填充以形成大致半圆柱形或圆柱形的导线。与具有成角度的边缘的传统矩形导体相比，基本上半圆柱形导线的圆形底部或基本上半圆柱形导线的圆形底部和顶部避免了用于开始电介质层中的裂纹的传播点，实际上是用于引发裂纹的传播点。基本上半圆柱形或圆柱形的线还减少相邻导线之间的线间电容，基本上消除了介电层中的任何高应力点，减小了在IC上引起的机械应力并增加了IC的整体机械强度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式