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21. 发明授权

US06989385B2 Pyrazole compounds useful as protein kinase inhibitors 失效
标题翻译：用作蛋白激酶抑制剂的吡唑化合物
公开(公告)号：US06989385B2
公开(公告)日：2006-01-24
申请号：US10026967
申请日：2001-12-19
申请人： David Bebbington , Jean-Damien Charrier , Robert Davies , Simon Everitt , David Kay , Ronald Knegtel , Sanjay Patel
发明人： David Bebbington , Jean-Damien Charrier , Robert Davies , Simon Everitt , David Kay , Ronald Knegtel , Sanjay Patel
IPC分类号： C07D403/12 , A61K31/517 , A61K31/519
CPC分类号： C07D403/14 , C07D231/12 , C07D233/56 , C07D249/08 , C07D401/12 , C07D401/14 , C07D403/12 , C07D405/14 , C07D407/14 , C07D409/14 , C07D417/14 , C07D471/04 , C07D473/16 , C07D487/04 , C07D491/04 , C07D493/04 , C07D495/04 , C07D513/04
摘要： This invention describes novel pyrazole compounds of formula IIc: wherein R1 is T-Ring D, wherein Ring D is a 5-7 membered monocyclic ring or 8-10 membered bicyclic ring selected from aryl, heteroaryl, heterocyclyl or carbocyclyl; Rx and Ry are taken together with their intervening atoms to form a fused, unsaturated or partially unsaturated, 5-7 membered ring having 0-3 heteroatoms; and R2 and R2′ are as described in the specification. The compounds are useful as protein kinase inhibitors, especially as inhibitors of Aurora-2 and GSK-3, for treating diseases such as cancer, diabetes and Alzheimer's disease.
摘要翻译：本发明描述了式IIc的新的吡唑化合物：其中R 1是T环D，其中环D是5-7元单环或8-10元双环，其选自芳基，杂芳基，杂环基或碳环基; R x和R y与它们的插入原子一起形成具有0-3个杂原子的稠合的，不饱和的或部分不饱和的5-7元环; 和R 2和R 2'如说明书中所述。这些化合物可用作蛋白激酶抑制剂，特别是作为Aurora-2和GSK-3的抑制剂用于治疗诸如癌症，糖尿病和阿尔茨海默病的疾病。

22. 发明授权

US06256729B1 Method and apparatus for resolving multiple branches 失效
标题翻译：用于解决多个分支的方法和装置
公开(公告)号：US06256729B1
公开(公告)日：2001-07-03
申请号：US09004971
申请日：1998-01-09
申请人： Rajasekhar Cherabuddi , Sanjay Patel , Adam R. Talcott , Ramesh K. Panwar
发明人： Rajasekhar Cherabuddi , Sanjay Patel , Adam R. Talcott , Ramesh K. Panwar
IPC分类号： G06F1500
CPC分类号： G06F9/3861 , G06F9/3806
摘要： A method for repairing a pipeline in response to a branch instruction having a branch, includes the steps of providing a branch repair table having a plurality of entries, allocating an entry in the branch repair table for the branch instruction, storing a target address, a fall-through address, and repair information in the entry in the branch repair table, processing the branch instruction to determine whether the branch was taken, and repairing the pipeline in response to the repair information and the fall-through address in the entry in the branch repair table when the branch was not taken.
摘要翻译：一种用于响应于具有分支的分支指令来修复流水线的方法，包括以下步骤：提供具有多个条目的分支修复表，在分支指令的分支修复表中分配条目，存储目标地址，分支修复表中的条目中的修复信息和修复信息，处理分支指令以确定是否采用分支，以及修复管道，以响应修复信息和条目中的到达地址分支修复表时未分支。

23. 发明授权

US6085721A Bar engine brake 失效
标题翻译：酒吧发动机制动
公开(公告)号：US6085721A
公开(公告)日：2000-07-11
申请号：US145243
申请日：1998-09-02
申请人： Sotir Dodi , Ronald B. Wahl , David Courcy , Sanjay Patel
发明人： Sotir Dodi , Ronald B. Wahl , David Courcy , Sanjay Patel
IPC分类号： F01L13/06 , F02D13/04
CPC分类号： F01L13/06
摘要： The present invention is directed to a control system for controlling operation of an engine compression release brake for an engine. The control system includes a valve actuation assembly for actuating at least one valve during a predetermined engine operating condition. The control system also includes an energy supply assembly for supplying energy to operate the valve actuation assembly. The control system includes a control assembly for controlling the operation of valve actuation assembly.
摘要翻译：本发明涉及一种用于控制用于发动机的发动机压缩释放制动器的操作的控制系统。控制系统包括用于在预定发动机操作状态期间致动至少一个阀的阀致动组件。控制系统还包括用于提供能量以操作阀致动组件的能量供应组件。控制系统包括用于控制阀致动组件的操作的控制组件。

24. 发明授权

US5944866A Fabrication including sol-gel processing 失效
标题翻译：制作包括溶胶 - 凝胶加工
公开(公告)号：US5944866A
公开(公告)日：1999-08-31
申请号：US89859
申请日：1998-06-03
申请人： You-Lung Chen , Sanjay Patel , Jorge Luis Valdes
发明人： You-Lung Chen , Sanjay Patel , Jorge Luis Valdes
IPC分类号： C03B8/02 , C03B20/00 , C03B37/012 , C03C1/00 , C03B37/016
CPC分类号： C03C1/006 , Y10S65/901
摘要： The invention provides an alternative to conventional sol-gel methods that utilize undesirably high amounts of a stabilizing agent such as TMAH and a gelling agent such as methyl formate. The method involves the steps of (a) providing a colloidal silica dispersion containing a stabilizing/gelling agent, where only a portion of the molecules of the agent ionize, and (b) subsequently adding to the silica dispersion a pH-reducing additive. The stabilizing/gelling agent has a dual function. The agent, e.g., an amine, initially acts as a stabilizer in the silica dispersion in that a portion of its molecules ionize, while an appreciable amount of the agent remains non-ionized. The agent later transforms in situ to a gelling agent upon addition of a pH-reducing additive. Specifically, as the pH-reducing additive lowers the pH to values at or around the pK.sub.a of the stabilizing/gelling agent, more of the agent's molecules are ionized, these cations contributing to charge neutralization, and thus gellation, of the colloidal silica particles.
摘要翻译：本发明提供了常规溶胶 - 凝胶方法的替代方案，其使用不希望的大量稳定剂如TMAH和胶凝剂如甲酸甲酯。该方法包括以下步骤：（a）提供含有稳定/胶凝剂的胶态二氧化硅分散体，其中只有一部分试剂的分子离子化，和（b）随后向二氧化硅分散体中加入pH降低添加剂。稳定剂/胶凝剂具有双重功能。该试剂，例如胺最初充当二氧化硅分散体中的稳定剂，因为其一部分分子离子化，而相当量的试剂保持非离子化。该添加剂随后在添加pH降低添加剂时原位转化为胶凝剂。具体地说，随着pH值降低添加剂将pH降低至稳定/胶凝剂的pKa值或周围值，离子化剂的分子越多，这些阳离子有助于胶体二氧化硅颗粒的电荷中和，从而凝胶化。

25. 发明授权

US5938761A Method and apparatus for branch target prediction 失效
标题翻译：分支目标预测方法和装置
公开(公告)号：US5938761A
公开(公告)日：1999-08-17
申请号：US976826
申请日：1997-11-24
申请人： Sanjay Patel , Adam R. Talcott , Rajasekhar Cherabuddi
发明人： Sanjay Patel , Adam R. Talcott , Rajasekhar Cherabuddi
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3806
摘要： One embodiment of the present invention provides a method and an apparatus for predicting the target of a branch instruction. This method and apparatus operate by using a translation lookaside buffer (TLB) to store page numbers for predicted branch target addresses. In this embodiment, a branch target address table stores a small index to a location in the translation lookaside buffer, and this index is used retrieve a page number from the location in the translation lookaside buffer. This page number is used as the page number portion of a predicted branch target address. Thus, a small index into a translation lookaside buffer can be stored in a predicted branch target address table instead of a larger page number for the predicted branch target address. This technique effectively reduces the size of a predicted branch target table by eliminating much of the space that is presently wasted storing redundant page numbers. Another embodiment maintains coherence between the branch target address table and the translation lookaside buffer. This makes it possible to detect a miss in the translation lookaside buffer at least one cycle earlier by examining the branch target address table.
摘要翻译：本发明的一个实施例提供了一种用于预测分支指令的目标的方法和装置。该方法和装置通过使用翻译后备缓冲器（TLB）来存储用于预测的分支目标地址的页码。在本实施例中，分支目标地址表将小索引存储到翻译后备缓冲器中的位置，并且使用该索引从翻译后备缓冲器中的位置检索页码。该页码用作预测分支目标地址的页码部分。因此，可以在预测的分支目标地址表中存储向翻译后备缓冲器的小索引，而不是预测的分支目标地址的较大的页码。该技术通过消除存储冗余页码的目前浪费的大部分空间来有效地减小预测分支目标表的大小。另一个实施例维护分支目标地址表和转换后备缓冲器之间的一致性。这使得可以通过检查分支目标地址表来更早地检测翻译后备缓冲区中的未命中至少一个周期。

26. 发明授权

US5854761A Cache memory array which stores two-way set associative data 失效
标题翻译：存储双向组关联数据的缓存存储器阵列
公开(公告)号：US5854761A
公开(公告)日：1998-12-29
申请号：US883544
申请日：1997-06-26
申请人： Sanjay Patel , Rajasekhar Cherabuddi , Ramesh Panwar , Adam R. Talcott
发明人： Sanjay Patel , Rajasekhar Cherabuddi , Ramesh Panwar , Adam R. Talcott
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10
CPC分类号： G11C7/00 , G06F12/0864 , G06F12/0886 , G11C7/1042
摘要： A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.
摘要翻译：缓存存储器阵列存储双向组关联数据。奇数组数据组存储奇数组合的双向组关联数据，其中每个奇数组的两种方式在奇数组数据库内水平排列。偶数集数据库存储偶数集合的双向组关联数据，其中每个偶数集合的两个方式在偶数集数据库内水平对准。此外，奇数组数据组与偶数组数据组水平对准，使得每个奇数组都与下一个偶数组水平对准。水平对齐的方式被交织以减少数据路径宽度。设置和路径选择电路从数组中提取数据行。阵列可以在结构上由单端口RAM单元实现。

27. 发明公开

US20240225216A9 UMBRELLA CASE 审中-公开
公开(公告)号：US20240225216A9
公开(公告)日：2024-07-11
申请号：US17768849
申请日：2020-09-08
申请人： Sanjay Patel , Rachel GRIMALDI
发明人： Sanjay Patel , Rachel GRIMALDI
IPC分类号： A45B25/24 , A45F3/02
CPC分类号： A45B25/24 , A45F3/02 , A45F2003/003
摘要： An umbrella case configured to hold an umbrella having a rigid shaft with a handle at one end and a spike at the other end, the umbrella case comprising an umbrella holding assembly comprising a generally tubular sheath 106 having an open end and a spike-receiving portion 107 defining a spike-receiving aperture at the other end, and a fastening strap 100 having a first end coupled to an outer surface of the umbrella case, close to the open end of the sheath 106, and having a second, free end configured to be selectively moved to a fastening position in which it is connected to the umbrella case at a generally diametrically opposite location to the first end, the sheath, the spike-receiving portion and the fastening strap when in the fastening position, together, defining the effective length of the umbrella holding assembly, wherein at least one of the sheath, the spike-receiving portion and the fastening strap is selectively longitudinally extendible upon application of a force, in use, thereby to increase the effective length of the umbrella holding assembly to accommodate the length of an umbrella held therein.

28. 发明公开

US20240130492A1 UMBRELLA CASE 审中-公开
公开(公告)号：US20240130492A1
公开(公告)日：2024-04-25
申请号：US17768849
申请日：2020-09-07
申请人： Sanjay Patel , Rachel GRIMALDI
发明人： Sanjay Patel , Rachel GRIMALDI
IPC分类号： A45B25/24 , A45F3/02
CPC分类号： A45B25/24 , A45F3/02 , A45F2003/003
摘要： An umbrella case configured to hold an umbrella having a rigid shaft with a handle at one end and a spike at the other end, the umbrella case comprising an umbrella holding assembly comprising a generally tubular sheath 106 having an open end and a spike-receiving portion 107 defining a spike-receiving aperture at the other end, and a fastening strap 100 having a first end coupled to an outer surface of the umbrella case, close to the open end of the sheath 106, and having a second, free end configured to be selectively moved to a fastening position in which it is connected to the umbrella case at a generally diametrically opposite location to the first end, the sheath, the spike-receiving portion and the fastening strap when in the fastening position, together, defining the effective length of the umbrella holding assembly, wherein at least one of the sheath, the spike-receiving portion and the fastening strap is selectively longitudinally extendible upon application of a force, in use, thereby to increase the effective length of the umbrella holding assembly to accommodate the length of an umbrella held therein.

29. 发明授权

US08639885B2 Reducing implementation costs of communicating cache invalidation information in a multicore processor 有权
标题翻译：降低在多核处理器中传送缓存无效信息的实施成本
公开(公告)号：US08639885B2
公开(公告)日：2014-01-28
申请号：US12643238
申请日：2009-12-21
申请人： Prashant Jain , Sandip Das , Sanjay Patel
发明人： Prashant Jain , Sandip Das , Sanjay Patel
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , Y02D10/13
摘要： A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存，其中每个更高级别的高速缓存包括更高级别的高速缓存行; 以及包括较低级别高速缓存行的下级缓存，其中每个下级高速缓存行可以被配置为存储对应于多个更高级别的高速缓存行的数据。响应于使给定的低级高速缓存行无效，低级缓存可以被配置为经由接口将包括若干无效分组的序列传送到处理器核，其中无效分组序列中的每个成员对应于相应较高的高级缓存行将被无效，并且其中接口比能够同时传送对应于给定下级高速缓存行的所有无效信息的接口更窄。每个无效分组可以包括指示相应的较高级别高速缓存行在不同处理器核心内的位置的无效信息。

30. 发明申请

US20130263124A1 Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine 有权
标题翻译：虚拟机中访客和根注册器共享的装置和方法
公开(公告)号：US20130263124A1
公开(公告)日：2013-10-03
申请号：US13436654
申请日：2012-03-30
申请人： Sanjay Patel , Ranjit Joseph Rozario
发明人： Sanjay Patel , Ranjit Joseph Rozario
IPC分类号： G06F9/455
CPC分类号： G06F9/4555
摘要： A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.
摘要翻译：计算机可读存储介质包括可执行指令，以定义具有访客模式控制寄存器的处理器，所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定访客模式控制寄存器包括一个控制位，用于指定访客阻止寄存器状态和共享寄存器状态。根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。访客环境和根本环境支持硬件资源的虚拟化，使得支持多个应用的多个操作系统由硬件资源执行。

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