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21. 发明申请

US20060034112A1 Data read circuit for use in a semiconductor memory and a method therefor 有权
标题翻译：用于半导体存储器的数据读取电路及其方法
公开(公告)号：US20060034112A1
公开(公告)日：2006-02-16
申请号：US11249858
申请日：2005-10-13
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C7/06 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2207/005
摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要翻译：提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

22. 发明申请

US20060028886A1 Control of set/reset pulse in response to peripheral temperature in PRAM device 有权
标题翻译：根据PRAM器件的外围温度控制置位/复位脉冲
公开(公告)号：US20060028886A1
公开(公告)日：2006-02-09
申请号：US11124341
申请日：2005-05-06
申请人： Byung-Gil Choi , Choong-Keun Kwak , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Woo-Yeong Cho
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C7/1078 , G11C7/1096 , G11C13/0004 , G11C2013/0078
摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.
摘要翻译：用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。在另一个例子中，温度补偿器减小了较高外围温度的宽度。

23. 发明申请

US20060274574A1 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US20060274574A1
公开(公告)日：2006-12-07
申请号：US11502563
申请日：2006-08-11
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C2013/0078 , G11C2013/0092
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

24. 发明授权

US07851878B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07851878B2
公开(公告)日：2010-12-14
申请号：US12507504
申请日：2009-07-22
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

25. 发明授权

US07582941B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07582941B2
公开(公告)日：2009-09-01
申请号：US11480242
申请日：2006-06-30
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

26. 发明授权

US07245543B2 Data read circuit for use in a semiconductor memory and a method therefor 有权
标题翻译：用于半导体存储器的数据读取电路及其方法
公开(公告)号：US07245543B2
公开(公告)日：2007-07-17
申请号：US11249858
申请日：2005-10-13
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2207/005
摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要翻译：提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

27. 发明申请

US20050030814A1 Data read circuit for use in a semiconductor memory and a method thereof 有权
标题翻译：用于半导体存储器的数据读取电路及其方法
公开(公告)号：US20050030814A1
公开(公告)日：2005-02-10
申请号：US10943300
申请日：2004-09-17
申请人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
发明人： Hyung-Rok Oh , Woo-Yeong Cho , Choong-Keun Kwak
IPC分类号： G11C13/00 , G11C7/06 , G11C7/12 , G11C13/02 , G11C16/02 , G11C16/26 , H01L27/105 , H01L45/00 , G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C2013/0054 , G11C2207/005
摘要： A data read circuit and method for use in a semiconductor memory device that has a memory cell array are provided. The circuit includes a selector for selecting a unit cell within the memory cell array in response to an address signal; a clamping unit for supplying a clamp voltage having a level for a read operation to a bit line of the selected unit cell in response to a clamp control signal; a precharge unit for precharging a sensing node to a voltage having a power source level in response to a control signal of a first state in a precharge mode, and compensating through the sensing node for a reduced quantity of current at the bit line in response to a control signal of a second state in a data sensing mode; and a sense amplifier unit for comparing a level of the sensing node with a reference level, and for sensing data stored in the selected unit cell.
摘要翻译：提供了一种用于具有存储单元阵列的半导体存储器件中的数据读取电路和方法。该电路包括：选择器，用于响应于地址信号选择存储单元阵列内的单位单元; 夹紧单元，用于响应于钳位控制信号，将具有用于读取操作的电平的钳位电压提供给所选择的单位单元的位线; 预充电单元，用于响应于在预充电模式中的第一状态的控制信号，将感测节点预充电到具有电源电平的电压，并且响应于位线在位线处减少的电流量补偿在数据感测模式中的第二状态的控制信号; 以及感测放大器单元，用于将感测节点的电平与参考电平进行比较，并且用于感测存储在所选择的单位单元中的数据。

28. 发明授权

US6026039A Parallel test circuit for semiconductor memory 有权
标题翻译：半导体存储器的并行测试电路
公开(公告)号：US6026039A
公开(公告)日：2000-02-15
申请号：US215576
申请日：1998-12-17
申请人： Du-Eung Kim , Choong-Keun Kwak , Yun-Seung Shin
发明人： Du-Eung Kim , Choong-Keun Kwak , Yun-Seung Shin
IPC分类号： H01L21/822 , G01R31/26 , G01R31/28 , G11C29/02 , G11C29/50 , H01L27/04 , G11C7/00
CPC分类号： G11C29/022 , G11C29/02 , G11C29/50 , G11C2029/2602 , G11C2029/5006
摘要： A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.
摘要翻译：一种用于半导体存储器件的并行测试电路包括多个数据输入焊盘，分别连接到数据输入焊盘的多个数据输入缓冲器，用于在正常操作期间响应芯片选择信号接收写入数据;以及切换电路，用于电连接数据响应于施加到电路的电流泄漏测试信号，输入焊盘彼此相连。该电路能够在执行并行数据写入测试的同时检测输入数据缓冲器中的漏电流，从而减少测试器件所需的总时间。

29. 发明授权

US5959907A Semiconductor memory device having a redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器件
公开(公告)号：US5959907A
公开(公告)日：1999-09-28
申请号：US28150
申请日：1998-02-23
申请人： Du-Eung Kim , Choong-Keun Kwak
发明人： Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C29/04 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C11/418 , G11C29/785 , G11C29/83
摘要： A redundancy circuit for a semiconductor device comprises a circuit having variable impedance changed in accordance with a chip selecting signal. The variable impedance circuit has a low impedance when the chip selecting signal is at a low level and a high impedance when the chip selecting signal is at a high level. Therefore, when the device is in a standby state, no static current flows, and when the chip is in an active state current of less than several micro amperes flows. Thus, the power dissipation of the redundancy circuit can be reduced.
摘要翻译：用于半导体器件的冗余电路包括根据芯片选择信号而改变可变阻抗的电路。当芯片选择信号处于低电平时，可变阻抗电路具有低阻抗，并且当芯片选择信号处于高电平时具有高阻抗。因此，当器件处于待机状态时，不会流动静电流，并且当芯片处于活动状态时，电流小于几微安流动。因此，可以减少冗余电路的功率消耗。

30. 发明授权

US07110286B2 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US07110286B2
公开(公告)日：2006-09-19
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

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