专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06700814B1 Sense amplifier bias circuit for a memory having at least two distinct resistance states 有权
标题翻译：用于具有至少两个不同电阻状态的存储器的感测放大器偏置电路
公开(公告)号：US06700814B1
公开(公告)日：2004-03-02
申请号：US10283622
申请日：2002-10-30
申请人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
IPC分类号： G11C1100
CPC分类号： G11C7/06 , G11C2207/063
摘要： In a memory, a bias circuit (112, 212, 312, 412) uses a current reference (108) for providing a reference current and control circuitry (106, 120) to bias a sense amplifier (114) with a varying voltage (VB). The varying voltage maintains current through MRAM bit cells (177-179) at a value proportional to the reference current over variations in average bit cell resistance with immunity to variations in process, supply voltage and temperature. In one form, a mock sense amplifier (122, 126, 132, 134) and mock array of bit cells (130, 136) are used to establish internal steady state voltages equivalent to a steady state condition of the sense amplifier with equalized outputs and to generate the varying bias voltage. Matching diode-connected transistors in each of the control circuitry and either the mock sense amplifier or the sense amplifier is used to generate the varying bias voltage.
摘要翻译：在存储器中，偏置电路（112,212,312,412）使用电流参考（108）来提供参考电流和控制电路（106,120）以使具有变化电压（VB）的读出放大器（114）偏置）。变化的电压通过MRAM位单元（177-179）保持与参考电流成比例的值，与平均位单元电阻的变化相反，具有对工艺，电源电压和温度变化的抗扰性。在一种形式中，使用模拟读出放大器（122,126,132,134）和位单元（130,136）的模拟阵列来建立与具有均衡输出的读出放大器的稳态条件相当的内部稳态电压，以产生变化的偏置电压。每个控制电路和模拟读出放大器或读出放大器中的匹配二极管连接的晶体管用于产生变化的偏置电压。

22. 发明授权

US06538940B1 Method and circuitry for identifying weak bits in an MRAM 失效
标题翻译：用于识别MRAM中弱位的方法和电路
公开(公告)号：US06538940B1
公开(公告)日：2003-03-25
申请号：US10255303
申请日：2002-09-26
申请人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
发明人： Joseph J. Nahas , Thomas W. Andre , Bradley J. Garni
IPC分类号： G11C700
CPC分类号： G11C29/12005 , G11C11/16 , G11C29/12
摘要： A memory (10, 60) having at least two resistance states is tested. In one form, the memory includes a first transistor (16, 68) having a current electrode coupled to a memory cell (14, 64) and a second transistor (26, 66) having a current electrode coupled to a reference memory cell (28, 74). The control electrode of the first transistor receives either a first reference voltage or a second reference voltage based on a test control signal, and the control electrode of a second transistor receives the first reference voltage. In a test mode, after the memory cell is programmed with a resistance state, the second reference voltage (different from the first reference voltage) is provided to the first transistor. The memory cell is then read to determine whether the memory can sense the previously programmed resistance state. In one embodiment, this test mode can be used to identify weak bits in the memory.
摘要翻译：测试具有至少两个电阻状态的存储器（10,60）。在一种形式中，存储器包括具有耦合到存储器单元（14,64）的电流电极的第一晶体管（16,68）和具有耦合到参考存储器单元（28）的电流电极的第二晶体管（26,66），74）。第一晶体管的控制电极基于测试控制信号接收第一参考电压或第二参考电压，并且第二晶体管的控制电极接收第一参考电压。在测试模式中，在存储单元被编程为电阻状态之后，将第二参考电压（不同于第一参考电压）提供给第一晶体管。然后读取存储器单元以确定存储器是否可以感测到先前编程的电阻状态。在一个实施例中，该测试模式可用于识别存储器中的弱位。

23. 发明授权

US06894937B2 Accelerated life test of MRAM cells 失效
标题翻译： MRAM细胞加速寿命试验
公开(公告)号：US06894937B2
公开(公告)日：2005-05-17
申请号：US10672959
申请日：2003-09-26
申请人： Bradley J. Garni , Thomas W. Andre , Joseph J. Nahas
发明人： Bradley J. Garni , Thomas W. Andre , Joseph J. Nahas
IPC分类号： G11C11/15 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/16 , G11C2029/5002
摘要： A circuit provides a stress voltage to magnetic tunnel junctions (MTJs), which comprise the storage elements of a magnetoresitive random access memory (MRAM), during an accelerated life test of the MRAM. The stress voltage is selected to provide a predetermined acceleration of aging compared to normal operation. A source follower circuit is used to apply a stress voltage to a subset of the memory cells at given point in time during the life test. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed. The result is a closely defined voltage applied to the MTJs so that the magnitude of the acceleration is well defined for all of the memory cells.
摘要翻译：在MRAM的加速寿命测试期间，电路向包括磁阻随机存取存储器（MRAM）的存储元件的磁隧道结（MTJ）提供应力电压。选择应力电压以提供与正常操作相比预定的老化加速度。源极跟随器电路用于在寿命测试期间的给定时间点将应力电压施加到存储器单元的子集。应力电压通过嘲笑存储器阵列部分的负载特性受到应力的电路保持在所需电压。结果是施加到MTJ的紧密定义的电压，使得对于所有存储器单元良好地限定加速度的大小。

24. 发明授权

US06888743B2 MRAM architecture 有权
标题翻译： MRAM架构
公开(公告)号：US06888743B2
公开(公告)日：2005-05-03
申请号：US10331058
申请日：2002-12-27
申请人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
发明人： Mark A. Durlam , Thomas W. Andre , Brian R. Butcher , Mark F. Deherrera , Bradley N. Engel , Bradley J. Garni , Gregory W. Grynkewich , Joseph J. Nahas , Nicholas D. Rizzo , Saied Tehrani , Clarance J. Tracy
IPC分类号： G11C11/15 , G11C11/02
CPC分类号： G11C11/16
摘要： An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.
摘要翻译：提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。

25. 发明授权

US5614816A Low voltage reference circuit and method of operation 失效
标题翻译：低电压参考电路和操作方法
公开(公告)号：US5614816A
公开(公告)日：1997-03-25
申请号：US560876
申请日：1995-11-20
申请人： Joseph J. Nahas
发明人： Joseph J. Nahas
IPC分类号： G05F3/30 , G05F3/24 , H03F1/30 , G05F3/16
CPC分类号： G05F3/245 , Y10S323/907
摘要： A voltage reference generator circuit (600) that operates at low voltages may be obtained by using a summation circuit (618) to combine a divided bipolar junction voltage signal (616) and a multiplied voltage signal (622) that is proportional to absolute temperature. The voltage reference generator circuit (600) generates a voltage reference which is divided by a divide circuit (620) which produces the divided signal (616), and a voltage reference which is multiplied by a multiply circuit (630) which produces the multiplied signal (622). In another form, a bipolar junction voltage and a voltage that is proportional to absolute temperature may be converted to currents and summed to provide a current which is converted into the reference voltage output.
摘要翻译：可以通过使用求和电路（618）来组合分压双极结电压信号（616）和与绝对温度成正比的倍增电压信号（622）来获得在低电压下工作的电压参考发生器电路（600）。电压基准发生器电路（600）生成由产生分频信号（616）的除法电路（620）分压的电压基准，以及乘以产生相乘信号的乘法电路（630）的电压基准（622）。在另一种形式中，双极结电压和与绝对温度成比例的电压可以转换为电流并相加以提供转换为参考电压输出的电流。

26. 发明授权

US4625078A Fraud prevention in an electronic coin telephone set 失效
标题翻译：电子硬币电话机中的欺诈预防
公开(公告)号：US4625078A
公开(公告)日：1986-11-25
申请号：US567053
申请日：1983-12-30
申请人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
发明人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
IPC分类号： G07D5/08 , G07F1/04 , G07F5/22 , H04M17/02
CPC分类号： G07F1/04 , H04M17/023
摘要： This invention pertains to a microcomputer controlled coin telephone set which prevents coin call fraud and performs all of the coin discrimination functions. The microcomputer also checks the operational readiness of the telephone set to prevent the acceptance of coins into a hopper for late collection by a coin box unless or until the set is fully functional.
摘要翻译：本发明涉及一种防止硬币通话欺诈并执行所有硬币鉴别功能的微计算机控制硬币电话机。微型计算机还检查电话机的操作准备状况，以防止将硬币接收到料斗中以便由硬币盒进行晚期收集，除非或者直到该组件完全起作用。

27. 发明授权

US07082389B2 Method and apparatus for simulating a magnetoresistive random access memory (MRAM) 失效
标题翻译：用于模拟磁阻随机存取存储器（MRAM）的方法和装置
公开(公告)号：US07082389B2
公开(公告)日：2006-07-25
申请号：US10302203
申请日：2002-11-22
申请人： Joseph J. Nahas
发明人： Joseph J. Nahas
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and apparatus (500) for simulating a magnetoresistive random access memory (MRAM) (102) uses non-linear functions to model both non-linear magnetic tunnel junction (MTJ) effects and non-linear state switching effects. The method includes calculating a high threshold (THI) and a low threshold (TLO) based on a function of the hard axis current (IH). The easy axis current (IE) is compared to the high threshold (THI). If the easy axis current is greater than the high threshold, the MTJ resistance (RHI) is set to represent a stored high value. The easy axis current is compared to the low threshold. If the easy axis current is less than the low threshold, the MTJ resistance (RLO) is set to represent a stored low value. By using non-linear functions to model the MTJ effects and switching effects, the behavior of an MRAM (102) can be more accurately simulated.
摘要翻译：用于模拟磁阻随机存取存储器（MRAM）（102）的方法和装置（500）使用非线性函数来模拟非线性磁隧道结（MTJ）效应和非线性状态切换效应。该方法包括基于硬轴电流（I H H）的函数来计算高阈值（T HI）和低阈值（T LO） SUB>）。将易轴电流（I E E）与高阈值（T HI）进行比较。如果容易轴电流大于高阈值，则将MTJ电阻（R SUB HI）设置为表示存储的高值。将易轴电流与低阈值进行比较。如果容易轴电流小于低阈值，则将MTJ电阻（R LO LO）设置为表示存储的低值。通过使用非线性函数来建模MTJ效应和切换效果，可以更精确地模拟MRAM（102）的行为。

28. 发明授权

US4674114A Fraud prevention in an electronic coin telephone set 失效
标题翻译：电子硬币电话机中的欺诈预防
公开(公告)号：US4674114A
公开(公告)日：1987-06-16
申请号：US882348
申请日：1986-07-07
申请人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
发明人： Paul E. Crouch , Joseph J. Nahas , Howard Ng
IPC分类号： G07F1/04 , H04M17/02 , H04M17/00
CPC分类号： G07F1/04 , H04M17/023
摘要： In an electronic coin telephone set, a fraud prevention arrangement prevents fraudulent coin tones originating at a telephone transmitter from being provided to a central office over a coin subscriber loop. The arrangement comprises a first and second transmission channel for alternately connecting the transmitter to the central office and also a fraud filter disposed in the second transmission channel. The fraud filter attenuates a selected frequency originating at the transmitter that is indicative of coin deposits. When coin deposits are not required by the central office, the transmitter is connected to the central office through the first transmission channel. When coin deposits are required by the central office, however, the arrangement connects the transmitter to the central office through the second transmission channel thereby avoiding the fraudulent generating of coin tones through the telephone transmitter.
摘要翻译：在电子硬币电话机中，防欺诈装置可以防止在电话发送器发起的欺诈性硬币通过硬币用户回路提供给中心局。该装置包括用于将发射机交替地连接到中心局的第一和第二传输信道，以及布置在第二传输信道中的欺诈过滤器。欺诈滤波器衰减起始于指示硬币存储的发射机的选定频率。当中央办公室不需要硬币存款时，发送器通过第一个传输通道连接到中心局。然而，当中心局需要硬币存款时，该装置通过第二传输信道将发射机连接到中心局，从而避免通过电话发射机欺骗性地产生硬币音。

29. 发明授权

US4357496A Keypad logic interface circuit 失效
标题翻译：键盘逻辑接口电路
公开(公告)号：US4357496A
公开(公告)日：1982-11-02
申请号：US202950
申请日：1980-11-30
申请人： Joseph J. Nahas
发明人： Joseph J. Nahas
IPC分类号： H04M1/50
CPC分类号： H04M1/505
摘要： A keypad logic interface circuit (200) provides a switch closure output signal representative of a selected one of a plurality of digits on a crosspoint contact array keypad (100). The selected one of the plurality of digits provides the switch closure signal by diverting a source current (225) from a first to a second direction. The circuit encodes each one of four column outputs from the keypad into a two-bit code. An output signal from two or more columns at the same time causes the circuit to produce an inhibit output signal reflecting a multiple button-push condition. The circuit also encodes each of four row outputs from the keypad into a two-bit code and produces an inhibit output signal when multiple row output signals are received.
摘要翻译：键盘逻辑接口电路（200）提供代表交叉点触点阵列键盘（100）上的多个数字中选定的一个的开关闭合输出信号。通过将源电流（225）从第一方向转移到第二方向，所述多个数字中的所选择的一个提供开关闭合信号。电路将键盘中四列输出中的每一列编码为两位代码。来自两个或更多个列的输出信号同时导致电路产生反映多个按钮推送状态的禁止输出信号。该电路还将从键盘的四行输出中的每一行编码为两位代码，并在接收到多行输出信号时产生禁止输出信号。

30. 发明授权

US4352958A Electronically-switched multifrequency generator with transducer control 失效
标题翻译：具有传感器控制的电子切换多频发生器
公开(公告)号：US4352958A
公开(公告)日：1982-10-05
申请号：US103403
申请日：1979-12-13
申请人： Paul C. Davis , Raymond G. Jackson , Joseph J. Nahas , Dale H. Nelson , DeWitt G. Ong , Brian A. Wittman
发明人： Paul C. Davis , Raymond G. Jackson , Joseph J. Nahas , Dale H. Nelson , DeWitt G. Ong , Brian A. Wittman
IPC分类号： H03K3/78 , H04M1/50
CPC分类号： H04M1/505
摘要： In a multifrequency generator providing tone signaling for a telephone, the common switching functions are performed by solid state switching circuitry (1200). Improved signal transfer between the telephone line and transmit and receive transducer of the telephone is provided by arranging the solid-state transmit and receive switches (1201, 1401) in a gain configuration to increase the level of the speech signal. The tone signals are digitally synthesized and use an integrated R-C oscillator (600) as a reference. Button down and button up debouncing of a contact closure signal from a single contact per button keypad is provided.
摘要翻译：在为电话提供音频信令的多频发生器中，公共切换功能由固态切换电路（1200）执行。通过将固态发送和接收开关（1201,1401）布置在增益配置中以提高语音信号的电平来提供电话线和电话的发送和接收换能器之间的改进的信号传送。音频信号是数字合成的，并使用集成的R-C振荡器（600）作为参考。提供按钮并按下按钮，从每个按钮小键盘的单个触点触发闭合信号的去抖动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式