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21. 发明申请

US20070096782A1 Method and apparatus for fail-safe and restartable system clock generation 失效
标题翻译：用于故障安全和可重启系统时钟生成的方法和装置
公开(公告)号：US20070096782A1
公开(公告)日：2007-05-03
申请号：US11260563
申请日：2005-10-27
申请人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
发明人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/04
摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.
摘要翻译：用于故障安全和可重新启动的系统时钟生成的方法和装置提供了由于错误的时钟发生器设置或边缘时钟分配组件导致的故障的恢复。在时钟发生器的输出与下游电路之间的时钟分配路径的某一点检测到时钟故障。如果检测到时钟故障，则可以使用可能是时钟发生器参考时钟的第二时钟来操作下游电路。时钟发生器可以是锁相环，然后重新启动下游电路被保证工作的预定环路滤波器电压，或者在时钟发生器的输出端上分频器设置，从而降低频率确保下游电路工作。因此，时钟发生器的参数可以在将时钟发生器的输出恢复到下行电路之前被确定并且确定操作条件。

22. 发明申请

US20060156043A1 Dynamic power and clock-gating method and circuitry 失效
标题翻译：动态功率和时钟门控方法和电路
公开(公告)号：US20060156043A1
公开(公告)日：2006-07-13
申请号：US11034556
申请日：2005-01-13
申请人： Ying Liu , Jente Kuang , Hung Ngo
发明人： Ying Liu , Jente Kuang , Hung Ngo
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.
摘要翻译：电源门控电路被置于“休眠模式”中，选择性地将电源轨两端门控，用于静态功率控制和用于动态功率控制的时钟分配。在包括上电时间，执行计算并将结果返回到以下电路的唤醒信号之后建立时间间隔M. 类似地，建立时间间隔N，其指示在电源门控电路返回到睡眠模式之前在返回结果之后等待多久以确保期望的性能。当将来需要一个电源门控电路时，它将发出一个唤醒信号和一个预定的估计时间K，用于接收下一个唤醒信号。通过分析在唤醒信号激活之后何时将电源门控电路返回到休眠模式的时间M，N和K进行判断。

23. 发明授权

US08093657B2 Circuit and methods to improve the operation of SOI devices 有权
标题翻译：电路和方法来改善SOI器件的运行
公开(公告)号：US08093657B2
公开(公告)日：2012-01-10
申请号：US12181007
申请日：2008-07-28
申请人： Roy Childs Flaker , Catherine O'Brien, legal representative , Scott Flaker, legal representative , Shirley A. Flaker, legal representative , Bruce Flaker, legal representative , Anne Flaker, legal representative , Heather Flaker, legal representative , Louis C. Hsu , Jente Kuang
发明人： Roy Childs Flaker , Louis C. Hsu , Jente Kuang
IPC分类号： H01L27/13
CPC分类号： G11C16/08 , H01L27/1203
摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.
摘要翻译：根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。在本发明的优选实施例中，提供了一种脉冲放电电路。这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。各个器件的整体体电阻对器件的电位影响最小。

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