专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08093657B2 Circuit and methods to improve the operation of SOI devices 有权
标题翻译：电路和方法来改善SOI器件的运行
公开(公告)号：US08093657B2
公开(公告)日：2012-01-10
申请号：US12181007
申请日：2008-07-28
申请人： Roy Childs Flaker , Catherine O'Brien, legal representative , Scott Flaker, legal representative , Shirley A. Flaker, legal representative , Bruce Flaker, legal representative , Anne Flaker, legal representative , Heather Flaker, legal representative , Louis C. Hsu , Jente Kuang
发明人： Roy Childs Flaker , Louis C. Hsu , Jente Kuang
IPC分类号： H01L27/13
CPC分类号： G11C16/08 , H01L27/1203
摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.
摘要翻译：根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。在本发明的优选实施例中，提供了一种脉冲放电电路。这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。各个器件的整体体电阻对器件的电位影响最小。

2. 发明授权

US07405982B1 Methods to improve the operation of SOI devices 有权
标题翻译：改善SOI器件运行的方法
公开(公告)号：US07405982B1
公开(公告)日：2008-07-29
申请号：US09588351
申请日：2000-06-07
申请人： Catherine O'Brien, legal representative , Scott Flaker, legal representative , Shirley A. Flaker, legal representative , Bruce Flaker, legal representative , Anne Flaker, legal representative , Heather Flaker, legal representative , Louis L. Hsu , Jente B. Kuang
发明人： Roy Childs Flaker
IPC分类号： G11C5/14
CPC分类号： G11C16/08 , H01L27/1203
摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.
摘要翻译：根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。在本发明的优选实施例中，提供了一种脉冲放电电路。这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。各个器件的整体体电阻对器件的电位影响最小。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式