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21. 发明申请

US20120322255A1 Metal Bump Formation 有权
标题翻译：金属凸块形成
公开(公告)号：US20120322255A1
公开(公告)日：2012-12-20
申请号：US13161303
申请日：2011-06-15
申请人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
发明人： Ming-Da Cheng , Chih-Wei Lin , Hsiu-Jen Lin , Tzong-Hann Yang , Wen-Hsiung Lu , Zheng-Yi Lim , Yi-Wen Wu , Chung-Shi Liu
IPC分类号： H01L21/768
CPC分类号： H01L24/11 , H01L21/6836 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68327 , H01L2224/11003 , H01L2224/111 , H01L2224/1133 , H01L2224/11462 , H01L2224/1147 , H01L2224/11825 , H01L2224/11849 , H01L2224/119 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13655 , H01L2224/13671 , H01L2224/13672 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/94 , H01L2224/97 , H01L2924/00014 , H01L2924/00012 , H01L2924/01029 , H01L2924/01083 , H01L2924/0103 , H01L2924/01047 , H01L2924/01082 , H01L2224/11
摘要： A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.
摘要翻译：提供一种用于形成金属凸块的系统和方法。一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。回流工艺用于将导电盖重新流到导电凸块中。

22. 发明授权

US08242011B2 Method of forming metal pillar 有权
标题翻译：金属柱形成方法
公开(公告)号：US08242011B2
公开(公告)日：2012-08-14
申请号：US13004376
申请日：2011-01-11
申请人： Zheng-Yi Lim , Yi-Wen Wu , Wen-Hsiung Lu , Chih-Wei Lin , Tzong-Huann Yang , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Zheng-Yi Lim , Yi-Wen Wu , Wen-Hsiung Lu , Chih-Wei Lin , Tzong-Huann Yang , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/1147 , H01L2224/1181 , H01L2224/11824 , H01L2224/11827 , H01L2224/11849 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13565 , H01L2224/1357 , H01L2224/13583 , H01L2224/13693 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/01047 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/01073 , H01L2924/01049 , H01L2924/0103 , H01L2924/01025 , H01L2924/01022 , H01L2924/01032 , H01L2924/01078 , H01L2924/01012 , H01L2924/01013 , H01L2924/0104 , H01L2924/01046 , H01L2924/01082 , H01L2924/01029 , H01L2924/01083 , H01L2924/01051 , H01L2224/03 , H01L2224/11 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar.
摘要翻译：本公开涉及制造金属柱。制造半导体器件的示例性方法包括以下步骤：提供具有接触焊盘的衬底; 形成在所述衬底上延伸的钝化层，所述钝化层在所述接触焊盘上具有开口; 在所述接触焊盘和所述钝化层的一部分上形成金属柱; 在金属柱上形成焊料层; 并且使金属柱的侧壁与有机化合物反应，以在金属柱的侧壁上形成自组装单层或有机化合物的自组装多层。

23. 发明申请

US20110128481A1 DISPLAY DEVICE AND METHOD OF MEASURING SURFACE STRUCTURE THEREOF 有权
标题翻译：显示装置及其表面结构的测量方法
公开(公告)号：US20110128481A1
公开(公告)日：2011-06-02
申请号：US12779915
申请日：2010-05-13
申请人： Chih-Wei Lin , Min-Cheng Wang , Yung-Cheng Chen , Hung-Min Liu
发明人： Chih-Wei Lin , Min-Cheng Wang , Yung-Cheng Chen , Hung-Min Liu
IPC分类号： G02F1/1335 , G02F1/167 , G01B11/00
CPC分类号： G01B11/24 , G01B5/061 , G01B11/00 , G01B11/02 , G01B11/0608 , G01B11/08 , G01B17/02 , G02F1/133512 , G02F1/13394 , G03F7/70625
摘要： A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.
摘要翻译：提供显示装置和测量其表面结构的方法。显示装置包括第一和第二基板，第一和第二图案化遮光层以及第一和第二像素单元。设置在第一基板的表面上的第一图案化遮光层包括第一开口。设置在第一图案化遮光层中的第一基板的表面上的第二图案遮光层包括第二开口。第一像素单元包括第一和第二突起。第一突起相应地覆盖第一开口和第一图案化遮光层的一部分。第二突起设置在第一和第二图案化的遮光层中。第二像素单元包括对应地覆盖第二开口的第三突起和第二图案化遮光层的一部分，其中第二开口的尺寸小于第一开口的尺寸。

24. 发明申请

US20100270604A1 Non-Volatile Memories and Methods of Fabrication Thereof 有权
标题翻译：非易失性记忆及其制作方法
公开(公告)号：US20100270604A1
公开(公告)日：2010-10-28
申请号：US12714194
申请日：2010-02-26
申请人： Chih-Wei Lin , Yi-Fang Lee , Cheng-Ta Wu , Cheng-Yuan Tsai
发明人： Chih-Wei Lin , Yi-Fang Lee , Cheng-Ta Wu , Cheng-Yuan Tsai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/7881
摘要： Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode.
摘要翻译：描述了非易失性存储器及其制造方法。在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成氧化物层，并将氧化物层暴露于第一氮化步骤以形成第一富氮区域。第一富氮区域设置在氧化物层和半导体衬底之间的界面附近。在第一次氮化步骤之后，将氧化物层暴露于第二氮化步骤以形成第二富氮区域。第一栅电极形成在氧化物层上，其中第二富氮区邻近氧化物层和第一栅电极之间的界面设置。

25. 发明申请

US20080191297A1 WAFER LEVEL IMAGE SENSOR PACKAGE WITH DIE RECEIVING CAVITY AND METHOD OF THE SAME 审中-公开
标题翻译：带有接收孔的滤波器水平图像传感器封装及其方法
公开(公告)号：US20080191297A1
公开(公告)日：2008-08-14
申请号：US11673701
申请日：2007-02-12
申请人： Wen-Kun Yang , Jui-Hsien Chang , Chih-Wei Lin , Chao-Nan Chou
发明人： Wen-Kun Yang , Jui-Hsien Chang , Chih-Wei Lin , Chao-Nan Chou
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L31/0203 , H01L2224/24227 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and a through holes structure formed there through, wherein a terminal pads are formed under the through holes structure and the substrate includes a conductive trace formed on a lower surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die and the through holes structure. Conductive bumps are coupled to the terminal pads. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.
摘要翻译：本发明提供一种封装结构，其包括：衬底，其具有形成在衬底的上表面内的管芯容纳空腔和形成在其上的通孔结构，其中端子焊盘形成在通孔结构下方，并且衬底包括导电痕迹形成在基底的下表面上。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在介电层上形成再分配金属层（RDL），并与管芯和通孔结构相连。导电凸块耦合到端子焊盘。在电介质层内形成一个开口和一个顶部保护层，以露出图像传感器芯片的芯片的微透镜区域。保护层（膜）涂覆在微透镜区域上，具有防水和防油性，以消除颗粒污染。可选地，在微透镜区域上形成具有涂覆的IR滤光器的透明盖，用于保护。

26. 发明申请

US20080142939A1 TOOLS STRUCTURE FOR CHIP REDISTRIBUTION AND METHOD OF THE SAME 审中-公开
标题翻译：用于芯片重新分配的工具结构及其相关方法
公开(公告)号：US20080142939A1
公开(公告)日：2008-06-19
申请号：US11609944
申请日：2006-12-13
申请人： Wen-Kun Yang , Chun-Hui Yu , Chih-Wei Lin
发明人： Wen-Kun Yang , Chun-Hui Yu , Chih-Wei Lin
IPC分类号： H01L23/12 , H01L21/58
CPC分类号： H01L24/96 , H01L21/6835 , H01L24/27 , H01L24/29 , H01L2221/68318 , H01L2221/68368 , H01L2224/29014 , H01L2224/2919 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01094 , H01L2924/0665 , H01L2924/09701 , H01L2924/10253 , H01L2924/00
摘要： The present invention discloses a tool structure for chip redistribution and method of chip redistribution. The tool structure comprises a base substrate, a separable adhesion film formed on the base substrate, and the patterned glues placed on the separable adhesion film for fixating the dice covered by the core paste materials formed on a fixed substrate. The fixed substrate is bonding on the core paste materials and dice to form the panel wafer. The method comprises printing the pluralities of patterned glues placed on the separable adhesion film and the bonding pluralities of dice covered by the core paste materials, and then, the fixed substrate is bonding on the core paste materials and pluralities of dice. The method further comprises curing and separating the glues and the pluralities of dice with the fixed substrate, and then cleaning the residual glues on the panel wafer (pluralities of dice).
摘要翻译：本发明公开了一种用于芯片再分配的工具结构和芯片再分配方法。工具结构包括基底基底，形成在基底基底上的可分离粘合膜，以及放置在可分离粘合膜上的图案化胶，用于固定由形成在固定基底上的芯糊材料覆盖的骰子。固定基板粘合在芯糊材料和芯片上以形成面板晶片。该方法包括印刷放置在可分离粘合膜上的多个图案化胶和由芯糊材料覆盖的多个骰子的接合，然后固定的基底粘合在芯糊材料和多个骰子上。该方法还包括用固定基板固化和分离胶水和多个骰子，然后清洁面板晶片上的残留胶（多个骰子）。

27. 发明授权

US07353077B2 Methods for optimizing die placement 有权
标题翻译：优化模具放置的方法
公开(公告)号：US07353077B2
公开(公告)日：2008-04-01
申请号：US11222374
申请日：2005-09-08
申请人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
发明人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
IPC分类号： G06F19/00
CPC分类号： G03F7/70433 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
摘要翻译：在具有计算系统的对准标记的晶片上优化管芯放置的方法包括在第一位置上在晶片上布置多个场。傻瓜插入在至少一个布置的场和对准标记之间并且相邻于晶片边缘插入。确定在第一位置在晶片上可制造的模具的总数。晶片位置相对于多个场的位置移动到第二位置，并且确定在第二位置处在晶片上可制造的模具的总数。比较了从第一和第二位置中的每一个的可制造模具的总数，并且具有较高数量的可制造模具的位置是最佳模具放置位置的候选者。然后评估总场数，虚拟人总数以及共享虚拟人总数，以确定最佳管桩位置。

28. 发明授权

US09768137B2 Stud bump structure for semiconductor package assemblies 有权
公开(公告)号：US09768137B2
公开(公告)日：2017-09-19
申请号：US13460412
申请日：2012-04-30
申请人： Meng-Tse Chen , Hsiu-Jen Lin , Chih-Wei Lin , Cheng-Ting Chen , Ming-Da Cheng , Chung-Shi Liu
发明人： Meng-Tse Chen , Hsiu-Jen Lin , Chih-Wei Lin , Cheng-Ting Chen , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/00 , H01L23/498 , H01L25/10 , H01L21/48 , H01L23/367
CPC分类号： H01L24/14 , H01L21/4853 , H01L23/3677 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/1134 , H01L2224/13076 , H01L2224/1308 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/14135 , H01L2224/14136 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73104 , H01L2224/73204 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/00012 , H01L2924/00014 , H01L2924/15331 , H01L2924/15787 , H01L2924/3512 , H01L2924/014 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

29. 发明授权

US09607921B2 Package on package interconnect structure 有权
公开(公告)号：US09607921B2
公开(公告)日：2017-03-28
申请号：US13349405
申请日：2012-01-12
申请人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
发明人： Wen-Hsiung Lu , Yi-Wen Wu , Chih-Wei Lin , Hsiu-Jen Lin , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/568 , H01L23/3114 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02331 , H01L2224/03823 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05082 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05548 , H01L2224/05564 , H01L2224/05567 , H01L2224/05611 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/10126 , H01L2224/11464 , H01L2224/1191 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/73104 , H01L2924/00014 , H01L2924/181 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

30. 发明授权

US09598772B2 Method for fabricating bump structure without UBM undercut 有权
公开(公告)号：US09598772B2
公开(公告)日：2017-03-21
申请号：US12761863
申请日：2010-04-16
申请人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Chung-Shi Liu
发明人： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Chung-Shi Liu
IPC分类号： H01L23/498 , H01L21/3205 , C23C18/16 , H01L23/00 , H01L23/31
CPC分类号： C23C18/1605 , C23C18/165 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/81447 , H01L2924/0002 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/01046 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

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