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21. 发明授权

US08841709B2 JFET device and method of manufacturing the same 有权
标题翻译： JFET器件及其制造方法
公开(公告)号：US08841709B2
公开(公告)日：2014-09-23
申请号：US13450373
申请日：2012-04-18
申请人： Wing Chor Chan , Chih Min Hu , Jeng Gong
发明人： Wing Chor Chan , Chih Min Hu , Jeng Gong
IPC分类号： H01L29/66
CPC分类号： H01L29/42316 , H01L29/1058 , H01L29/1075 , H01L29/808
摘要： A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.
摘要翻译：所公开的半导体器件包括形成在绝缘结构之上和衬底之上的半导体淀积层。该器件包括形成在半导体淀积层中的第一和第二注入区域之间的接触区域上的栅极。第一和第二注入区都具有第一导电类型，栅极具有第二导电类型。器件还可以包括形成在半导体淀积层下面的第二栅极。

22. 发明授权

US08264056B2 Schottky diode 有权
标题翻译：肖特基二极管
公开(公告)号：US08264056B2
公开(公告)日：2012-09-11
申请号：US12845925
申请日：2010-07-29
申请人： Chung Yu Hung , Chih Min Hu , Wing Chor Chan , Jeng Gong
发明人： Chung Yu Hung , Chih Min Hu , Wing Chor Chan , Jeng Gong
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812
CPC分类号： H01L29/872 , H01L29/402 , H01L29/423
摘要： A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced.
摘要翻译：肖特基二极管包括可以用作阴极的欧姆层和可以用作阳极的金属层，以及由在欧姆层和金属层之间延伸的半导体材料形成的漂移通道。漂移沟道包括与欧姆接触层相邻的重掺杂区域。漂移通道与金属层形成肖特基势垒。在肖特基二极管反向偏置的情况下，提供夹断机构来夹紧漂移通道。结果，在肖特基二极管的反向偏置条件下，金属层与欧姆接触层之间的饱和或漏电流的电平降低。

23. 发明授权

US06205013B1 Multi-layer metallization capacitive structure for reduction of the simultaneous switching noise in integrated circuits 失效
标题翻译：用于降低集成电路中同时开关噪声的多层金属化电容结构
公开(公告)号：US06205013B1
公开(公告)日：2001-03-20
申请号：US09055774
申请日：1998-04-06
申请人： Jeng Gong , Jiann-Shiun Torng , Sheng-Hsing Yang
发明人： Jeng Gong , Jiann-Shiun Torng , Sheng-Hsing Yang
IPC分类号： H01G4228
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multi-layer metallization capacitive structure is provided to a conductive line, such as a power line or signal transmission line in an integrated circuit, where the undesired effect of simultaneous switching noise (SSN) is adverse due to rapid switching of pulses in a digital signal. The multi-layer metallization capacitive structure can help reduce the SSN effect in the integrated circuit by providing at least one metallization layer which extends substantially beneath the conductive line; and at least one dielectric layer sandwiched between the power line and the metallization layer. The multi-layer metallization capacitive structure has an optimal effect if the metallization layer is designed to be precisely equal in width to the power line. The multi-layer metallization capacitive structure has an advantage over the prior art in that it can be formed together with the processing for forming multiple interconnects in the integrated circuit without the need to devise additional processes. Moreover, it requires a reduced layout area to implement as compared to the conventional on-chip capacitor.
摘要翻译：多层金属化电容结构被提供给诸如集成电路中的电力线或信号传输线的导线，其中同时开关噪声（SSN）的不期望的影响由于数字中的脉冲的快速切换而不利信号。多层金属化电容结构可以通过提供至少一个基本上在导线下方延伸的金属化层来帮助降低集成电路中的SSN效应; 以及夹在电源线和金属化层之间的至少一个电介质层。如果金属化层设计成与电力线的宽度精确地相等，则多层金属化电容结构具有最佳效果。多层金属化电容结构具有优于现有技术的优点，因为它可以与集成电路中形成多个互连的处理一起形成，而不需要设计额外的工艺。此外，与传统的片上电容器相比，它需要实现的布局面积减小。

24. 发明授权

US5966608A Method of forming high voltage device 失效
标题翻译：高压装置形成方法
公开(公告)号：US5966608A
公开(公告)日：1999-10-12
申请号：US85208
申请日：1998-05-27
申请人： Jeng Gong , Sheng-Hsing Yang
发明人： Jeng Gong , Sheng-Hsing Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7801 , H01L29/1095 , H01L29/66674 , H01L29/66712 , H01L29/7802 , H01L21/26506
摘要： A method of forming high voltage device. A first type semiconductor having at least a gate formed thereon is provided. A first ion implantation with a second type dopant is performed to form a first diffusion region in the semiconductor substrate. An oxide layer is formed on the semiconductor substrate. A second ion implantation with the second type dopant is performed to form a second diffusion region within the first diffusion region. A silicon nitride layer is formed on the oxide layer, through which an opening penetrates to exposed the oxide layer. A third ion implantation with the second type dopant is performed using the silicon nitride layer as a mask to form a third diffusion region within the second diffusion region. Drive-in is performed to deepen the third diffusion region. The silicon nitride layer is removed. The exposed oxide layer is transformed into a field oxide layer. A fourth ion implantation with a first type dopant is performed to form a fourth diffusion region as a source/drain region within the second diffusion region under a surface between the field oxide layer and the gate.
摘要翻译：一种形成高压装置的方法。提供了至少形成有栅极的第一类型半导体。执行具有第二类型掺杂剂的第一离子注入以在半导体衬底中形成第一扩散区域。在半导体基板上形成氧化物层。执行具有第二类型掺杂剂的第二离子注入以在第一扩散区域内形成第二扩散区域。在氧化物层上形成氮化硅层，开口穿过该氮化硅层露出氧化层。使用氮化硅层作为掩模来执行具有第二类型掺杂剂的第三离子注入，以在第二扩散区域内形成第三扩散区域。执行驱动以加深第三扩散区域。去除氮化硅层。将暴露的氧化物层转变成场氧化物层。执行具有第一类型掺杂剂的第四离子注入，以在场氧化物层和栅极之间的表面下形成作为第二扩散区域内的源极/漏极区域的第四扩散区域。

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