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21. 发明授权

US5751034A High dielectric constant barium-strontium-niobium oxides for integrated circuit applications 失效
标题翻译：用于集成电路应用的高介电常数钡 - 锶 - 铌氧化物
公开(公告)号：US5751034A
公开(公告)日：1998-05-12
申请号：US873827
申请日：1997-06-12
申请人： Joseph D. Cuchiaro , Vikram Joshi , Claudia P. DaCruz , John M. McNelis , Carlos A. Paz de Araujo
发明人： Joseph D. Cuchiaro , Vikram Joshi , Claudia P. DaCruz , John M. McNelis , Carlos A. Paz de Araujo
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L29/76
CPC分类号： H01L28/55 , H01L21/31691
摘要： A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z=10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.
摘要翻译：一种电荷存储装置，例如集成电路存储器，包括包含钡 - 锶 - 氧化铌的电介质。制备包含金属钡，锶和铌的液体前体并将其施加到铂电极上。将前体烘烤和退火以形成具有式BaxSryNbzO30的电介质，其中x = 1.3至3.5，y = 1.5至3.7，z = 10。然后形成顶部铂电极以提供存储单元电容器。 Ba2Sr3Nb10O30已经获得了迄今为止最佳的结果，其产生介电常数超过1000的存储单元电介质，对于高达5伏的电压，漏电流小于10-5安培/平方厘米。

22. 发明授权

US06924997B2 Ferroelectric memory and method of operating same 有权
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06924997B2
公开(公告)日：2005-08-02
申请号：US10381235
申请日：2001-09-25
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan , Yoshihisa Kato , Tatsuo Otsuki , Yasuhiro Shimada
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等）驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

23. 发明授权

US06370056B1 Ferroelectric memory and method of operating same 失效
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06370056B1
公开(公告)日：2002-04-09
申请号：US09523492
申请日：2000-03-10
申请人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Zheng Chen , Vikram Joshi , Myoungho Lim , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells, each containing an FeFET and a MOSFET, each of said FeFETs having a source, a drain, a substrate, and a gate, and each MOSFET having a pair of source/drains and a gate. The cells are arranged in an array comprising a plurality of rows and a plurality of columns. A gate line and a bit line are associated with each column, and a word line, a drain line, and a substrate line are associated with each row. One source/drain of each MOSFET is connected to its corresponding gate line; the other source/drain is connected to the gate of the FeFET in the cell. The gate of the MOSFET is connected to its corresponding word line which provides a write and erase enable signal. The drain of the FeFET is connected to its corresponding drain line, and the source of the FeFET is connected to its corresponding bit line. The substrate of each FeFET is connected to its corresponding substrate line. A read MOSFET is connected between a drain input and the drain line associated with each row. The gate of the read MOSFET is connected to an input for the read enable signal.
摘要翻译：一种铁电非易失性存储器，包括：多个存储单元，每个存储单元包含FeFET和MOSFET，每个所述FeFET具有源极，漏极，衬底和栅极，并且每个MOSFET具有一对源极/漏极和一个门。单元被布置成包括多行和多列的阵列。栅极线和位线与每列相关联，并且字线，漏极线和衬底线与每一行相关联。每个MOSFET的一个源极/漏极连接到其对应的栅极线; 另一个源极/漏极连接到电池中的FeFET的栅极。 MOSFET的栅极连接到提供写和擦除使能信号的相应字线。 FeFET的漏极连接到其对应的漏极线，并且FeFET的源极连接到其对应的位线。每个FeFET的衬底连接到其相应的衬底线。读取MOSFET连接在与每行相关联的漏极输入和漏极线之间。读取MOSFET的栅极连接到读使能信号的输入端。

24. 发明授权

US06373743B1 Ferroelectric memory and method of operating same 失效
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US06373743B1
公开(公告)日：2002-04-16
申请号：US09385308
申请日：1999-08-30
申请人： Zheng Chen , Myoungho Lim , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
发明人： Zheng Chen , Myoungho Lim , Vikram Joshi , Carlos A. Paz de Araujo , Larry D. McMillan
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric non-volatile memory comprising: a plurality of memory cells each containing a ferroelectric FET, each of said ferroelectric FETs having a source, a drain, a substrate, and a gate. The FETs are arranged in an array comprising a plurality of rows and a plurality of columns. There are a plurality of row select lines, each associated with one of the rows of said ferroelectric FETs, and a plurality of column select lines, each associated with one of the columns of ferroelectric FETs. Each of the sources is directly electrically connected to its associated row select line, and each of the drains is directly electrically connected to its associated column select line. The source and substrate of each FET are also directly electrically connected. A memory cell is read by connecting its row select line to ground, and its column select line to a small voltage. All the gates, and the row select lines of non-selected cells are open or connected to a high resistance source. Thus, the current in the selected column select line and row select line is a measure of the state of the selected cell. Each FET is fabricated using a self-aligned process so that no portion of a source/drain underlies the gate.
摘要翻译：一种铁电非易失性存储器，包括：各自含有铁电FET的多个存储单元，每个所述铁电FET具有源极，漏极，基板和栅极。 FET被布置成包括多个行和多个列的阵列。存在多个行选择线，每条线选择线与所述强电介质FET的行中的一条相关联，以及多个列选择线，每条列选择线与铁电FET中的一列相关联。每个源直接电连接到其相关联的行选择线，并且每个漏极直接电连接到其相关联的列选择线。每个FET的源极和衬底也直接电连接。通过将其行选择线连接到地来读取存储单元，并且其列选择线为小电压。所有的门和未选择的单元的行选择线是打开的或连接到高电阻源。因此，所选列选择行和行选择行中的电流是所选单元格的状态的度量。每个FET使用自对准工艺制造，使得源极/漏极的任何部分不在栅极之下。

25. 发明授权

US6037046A Multi-component electromagnetic wave absorption panels 失效
标题翻译：多分量电磁波吸收面板
公开(公告)号：US6037046A
公开(公告)日：2000-03-14
申请号：US782934
申请日：1997-01-13
申请人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
发明人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
IPC分类号： E04B1/92 , H01Q17/00 , B32B7/00 , H05K9/00
CPC分类号： E04B1/92 , H01Q17/00 , H01Q17/004 , H01Q17/007 , H01Q17/008 , Y10T428/24942 , Y10T428/252 , Y10T428/31507 , Y10T428/31544 , Y10T428/31678
摘要： An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer is multi-component structure, such as: a high dielectric constant layer and ferrite layer; a ferrite layer and a low dielectric constant layer; a ferrite and a polymer; a polymer and a material having a higher dielectric constant than the polymer; a ferroelectric, a ferrite, and a polymer; a ferrite, a polymer, and a high dielectric constant material; and a high dielectric constant material, a material in which the imaginary part of the permeability is greater than or equal to the real part of the permeability, and a low dielectric constant material. The invention also includes combinations of the above, such as: a high dielectric constant material, a ferrite, and a low dielectric constant material; and multiple layers of a ferrite and a polymer. The invention further includes the above structures and combinations with specific materials, such as a ferrite, a polymer, LSM, and a high dielectric constant material; and a ferrite, a polymer, and BST. The invention also includes: a multi-component absorber element having an effective real part of the permitivity, .epsilon.'.sub.eff, and an effective real part of the permeability, .mu.'.sub.eff, such that (.epsilon.'.sub.eff .mu.'.sub.eff).sup.1/2 .about.1/f over said range of frequencies, where f is the frequency of the incident wave; and a multi-component absorber element having an effective real part of the permitivity, .epsilon.'.sub.eff, that decreases with frequency.
摘要翻译：用于建筑结构的电磁波吸收面板包括保护砖层，吸收层，金属反射层和建筑物支撑层，例如混凝土。吸收层是多组分结构，如：高介电常数层和铁素体层; 铁素体层和低介电常数层; 铁氧体和聚合物; 聚合物和具有比聚合物更高的介电常数的材料; 铁电体，铁氧体和聚合物; 铁氧体，聚合物和高介电常数材料; 和高介电常数材料，其中导磁率的虚部大于或等于导磁率的实部的材料和低介电常数材料。本发明还包括上述的组合，例如：高介电常数材料，铁素体和低介电常数材料; 和多层铁素体和聚合物。本发明还包括上述结构和与特定材料的组合，例如铁氧体，聚合物，LSM和高介电常数材料; 和铁素体，聚合物和BST。本发明还包括：多组分吸收元件，其具有有效实部的介电常数εεeff和渗透率μeff的有效实部，使得（ε'eff mu eff）+ E，在所述频率范围内，1/2 + EE差分1 / f，其中f是入射波的频率; 以及多分量吸收元件，其具有随频率而减小的有效实部的ε，εeff。

26. 发明授权

US5853500A Method for fabricating thin films of barium strontium titanate without exposure to oxygen at high temperatures 失效
标题翻译：在高温下不暴露于氧气的钛酸钡锶薄膜的制造方法
公开(公告)号：US5853500A
公开(公告)日：1998-12-29
申请号：US896574
申请日：1997-07-18
申请人： Vikram Joshi , Carlos A. Paz de Araujo
发明人： Vikram Joshi , Carlos A. Paz de Araujo
IPC分类号： C23C18/12 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , B05D5/12
CPC分类号： H01L21/31691 , C23C18/1216 , C23C18/1225 , C23C18/1283
摘要： A liquid precursor containing barium, strontium, and titanium, is applied to a first electrode, dried in air at a first temperature of 160.degree. C. and then a second temperature of 400.degree. C., and annealed at a temperature of 800.degree. C. in nitrogen to form a thin film of barium strontium titanate. A second electrode is deposited and then the device is patterned to form a capacitor, and a second anneal is performed at a temperature of 800.degree. C. in nitrogen. In this manner, a high electronic quality thin film of barium strontium titanate is fabricated without a high-temperature oxygen anneal.
摘要翻译：将包含钡，锶和钛的液体前体施加到第一电极上，在160℃的第一温度，然后在第二温度400℃下在空气中干燥，并在800℃的温度下退火在氮气中形成钛酸钡锶薄膜。沉积第二电极，然后将器件图案化以形成电容器，并且在氮气中在800℃的温度下进行第二次退火。以这种方式，在没有高温氧退火的情况下制造钛酸锶钡的高电子质量薄膜。

27. 发明授权

US5853889A Materials for electromagnetic wave absorption panels 失效
标题翻译：电磁波吸收面板材料
公开(公告)号：US5853889A
公开(公告)日：1998-12-29
申请号：US782938
申请日：1997-01-13
申请人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
发明人： Vikram Joshi , Kenichi Kimura , Carlos A. Paz de Araujo , Hiroshi Kiyokawa
IPC分类号： E04B1/92 , H01Q17/00 , B32B9/00
CPC分类号： E04B1/92 , H01Q17/00 , H01Q17/004 , H01Q17/007 , H01Q17/008 , Y10S428/913 , Y10T428/12007 , Y10T428/12014 , Y10T428/163 , Y10T428/166 , Y10T428/24612 , Y10T428/24777 , Y10T428/24917 , Y10T428/31504 , Y10T428/31529
摘要： An electromagnetic wave absorption panel for use in building construction includes a protective tile layer, an absorber layer, a metal reflective layer, and a building support layer, such as concrete. The absorber layer utilizes novel materials including high dielectric constant materials, such as ABO.sub.3 type perovskites, layered superlattice materials, conducting oxides, and signet magnetics, ferroelectrics, such as ABO.sub.3 type perovskites and layered superlattice materials, garnets, a nickel-zinc ferrite, Ni.sub.0.4 Zn.sub.0.6 Fe.sub.2 O.sub.4, and polymer-ceramic composites of the above materials.
摘要翻译：用于建筑结构的电磁波吸收面板包括保护砖层，吸收层，金属反射层和建筑物支撑层，例如混凝土。吸收层采用新型材料，包括高介电常数材料，如ABO3型钙钛矿，层状超晶格材料，导电氧化物和印刷磁性材料，铁电体，如ABO3型钙钛矿和层状超晶格材料，石榴石，镍锌铁氧体，Ni0 .4Zn0.6Fe2O4，以及上述材料的聚合物 - 陶瓷复合材料。

28. 发明申请

US20060194348A1 Ferroelectric and high dielectric constant integrated circuit capacitors with three-dimensional orientation for high-density memories, and method of making the same 有权
标题翻译：用于高密度存储器的具有三维取向的铁电和高介电常数集成电路电容器及其制造方法
公开(公告)号：US20060194348A1
公开(公告)日：2006-08-31
申请号：US11411767
申请日：2006-04-26
申请人： Carlos Araujo , Larry McMillan , Narayan Solayappan , Vikram Joshi
发明人： Carlos Araujo , Larry McMillan , Narayan Solayappan , Vikram Joshi
IPC分类号： H01L21/00 , H01L29/94
CPC分类号： H01L27/11502 , C30B29/32 , C30B29/68 , G11C11/22 , H01L21/7687 , H01L23/642 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.
摘要翻译：三维（“3-D”）存储电容器包括底电极，铁电薄膜和符合绝缘体层的3-D表面的顶电极。电容面积大于电容器的水平占位面积。优选地，电容器的占地面积小于0.2nm 2，并且相应的电容面积通常在0.4nm±2nm至1.0nm 2范围内铁电薄膜优选具有不超过60nm的厚度。包括底电极，铁电薄膜和顶电极的电容器层压体优选具有不超过200nm的厚度。用于沉积厚度在30nm至90nm范围内的铁电薄膜的低热预算MOCVD方法包括在沉积顶电极之前的RTP处理和在沉积顶电极之后进行RTP处理并蚀刻铁电层。

29. 发明申请

US20050094457A1 Ferroelectric memory and method of operating same 审中-公开
标题翻译：铁电存储器和操作方法相同
公开(公告)号：US20050094457A1
公开(公告)日：2005-05-05
申请号：US10425257
申请日：2003-04-28
申请人： Zheng Chen , Vikram Joshi , Narayan Solayappan , Carlos Paz de Araujo , Larry McMillan
发明人： Zheng Chen , Vikram Joshi , Narayan Solayappan , Carlos Paz de Araujo , Larry McMillan
IPC分类号： G11C11/22 , H01L27/06 , H01L27/115 , H01L29/78 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/223 , H01L27/0629 , H01L29/78391
摘要： A ferroelectric memory includes a group of memory cells, each cell having a ferroelectric memory element, a drive line on which a voltage for writing information to the group of memory cells is placed, and a bit line on which information to be read out of the group of memory cells is placed. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. A preamplifier is connected between the memory cells and the bit line. A set switch is connected between the drive line and the memory cells, and a reset switch is connected to the memory cells in parallel with the preamplifier. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
摘要翻译：铁电存储器包括一组存储器单元，每个单元具有铁电存储元件，其上放置用于向存储单元组写入信息的电压的驱动线以及从该存储单元读出的信息的位线放置一组存储单元。通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。前置放大器连接在存储单元和位线之间。一个开关连接在驱动线和存储单元之间，复位开关与前置放大器并联连接到存储单元。在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

30. 发明授权

US06171934B2 Recovery of electronic properties in process-damaged ferroelectrics by voltage-cycling 失效
标题翻译：通过电压循环恢复工艺损坏的铁电体中的电子特性
公开(公告)号：US06171934B2
公开(公告)日：2001-01-09
申请号：US09144297
申请日：1998-08-31
申请人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
发明人： Vikram Joshi , Narayan Solayappan , Walter Hartner , G{umlaut over (u)}nther Schindler
IPC分类号： H01L21326
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal. The voltage-cycling recovery process obviates oxygen-recovery annealing, and it allows continued use of conventional hydrogen-rich plasma processes and forming-gas anneals without the risk of permanent damage to the ferroelectric thin film.
摘要翻译：形成含有金属氧化物铁电体薄膜的集成电路。进行电压循环恢复处理以逆转由氢引起的铁电性能的降低。通过施加电压幅度为1至15伏特的104至1011个电压周期来执行电压循环恢复过程。在30-200℃范围内的较高温度下进行电压循环，提高了回收率。优选地，金属氧化物薄膜包括层状超晶格材料。优选地，层状超晶格材料包括钽酸铋钽铋或铌酸铋钽酸铋。如果集成电路制造包括成形气体退火，则在成形气体退火之后执行电压循环恢复过程。电压循环恢复过程避免氧回收退火，并且其允许继续使用常规富氢等离子体工艺和形成气体退火，而不会对铁电薄膜造成永久损坏的风险。

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