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21. 发明授权

US5675186A Construction that prevents the undercut of interconnect lines in plasma metal etch systems 失效
标题翻译：防止等离子体金属蚀刻系统中的互连线的切割的结构
公开(公告)号：US5675186A
公开(公告)日：1997-10-07
申请号：US672683
申请日：1996-06-28
申请人： Lewis Shen , Sheshadri Ramaswami , Mark Chang , Robin Cheung
发明人： Lewis Shen , Sheshadri Ramaswami , Mark Chang , Robin Cheung
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/532 , H01L29/43
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.
摘要翻译：不需要化学计量的TixNy层被插入在钛或铝互连层之间，以在图案化和等离子体蚀刻的过程中提高粘附性并防止互连层的倒入和提升，以在衬底上形成互连线，例如氧化物。

22. 发明授权

US08445372B2 Selective silicide formation using resist etch back 有权
标题翻译：使用抗蚀剂回蚀的选择性硅化物形成
公开(公告)号：US08445372B2
公开(公告)日：2013-05-21
申请号：US12644457
申请日：2009-12-22
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/285 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

23. 发明申请

US20090111265A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK 有权
标题翻译：选择性硅化物形成使用电阻蚀刻
公开(公告)号：US20090111265A1
公开(公告)日：2009-04-30
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

24. 发明授权

US07256141B1 Interface layer between dual polycrystalline silicon layers 有权
标题翻译：双层多晶硅层之间的界面层
公开(公告)号：US07256141B1
公开(公告)日：2007-08-14
申请号：US11135492
申请日：2005-05-24
申请人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
发明人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
IPC分类号： H01L21/31
CPC分类号： H01L27/115 , H01L27/11568
摘要： A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.
摘要翻译： A结构接双晶硅层。该结构包括第一层多晶硅和形成在第一多晶硅层的表面上的金属界面层。该结构还包括形成在界面层的表面上的第二层多晶硅。

25. 发明申请

US20060049826A1 Optical cross-connect system 有权
标题翻译：光交叉连接系统
公开(公告)号：US20060049826A1
公开(公告)日：2006-03-09
申请号：US10469516
申请日：2002-03-01
申请人： Michael Daneman , Franklin Wall , Behrang Behin , Murali Chaparala , Mark Chang , Scott Dalton , Timothy Beerling , Stephen Panyko , Meng-Hsiung Kiang , Boris Kobrin , Chuang-Chia Lin
发明人： Michael Daneman , Franklin Wall , Behrang Behin , Murali Chaparala , Mark Chang , Scott Dalton , Timothy Beerling , Stephen Panyko , Meng-Hsiung Kiang , Boris Kobrin , Chuang-Chia Lin
IPC分类号： G01B7/14
CPC分类号： G02B6/3518 , G02B6/3546 , G02B6/356 , G02B6/357 , G02B6/3572 , G02B6/3584 , G02B26/0841
摘要： An optical cross-connect switch comprises a base (216), a flap (211) and one or more electrically conductive landing pads (222) connected to the flap (211). The flap (211) has a bottom portion that is movably coupled to the base (216) such that the flap (211) is movable with respect to a plane of the base (216) from a first orientation to a second orientation. The one or more landing pads (222) are electrically isolated from the flap (211) and electrically coupled to be equipotential with a landing surface.
摘要翻译：光学交叉连接开关包括底座（216），翼片（211）和连接到翼片（211）的一个或多个导电着陆垫（222）。翼片（211）具有可移动地联接到基部（216）的底部部分，使得翼片（211）能够相对于基部（216）的平面从第一方向移动到第二方向。一个或多个着陆垫（222）与翼片（211）电隔离并且电耦合以与着陆表面等电位。

26. 发明授权

US06764929B1 Method and system for providing a contact hole in a semiconductor device 失效
标题翻译：用于在半导体器件中提供接触孔的方法和系统
公开(公告)号：US06764929B1
公开(公告)日：2004-07-20
申请号：US10151625
申请日：2002-05-16
申请人： Angela Hui , Chi Chang , Mark Chang
发明人： Angela Hui , Chi Chang , Mark Chang
IPC分类号： H01L21425
CPC分类号： H01L21/76897 , H01L21/265
摘要： A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure. Due to the etch difference between the implant treated device and the non-treated surface, it is possible to etch down to the bottom of the semiconductor device without damaging the gate. Since the surface around the gate structure is treated, the etch stop layer etch at a much slower rate. Therefore, there is a much larger process margin for misalignment allowance and the contact size can be larger because the dielectric material and the surface treatment protects the gate area.
摘要翻译：公开了一种用于在半导体器件的结构之间提供接触孔的方法和系统。该方法和系统包括在半导体器件上蚀刻抗蚀剂材料以暴露结构的表面; 向所述结构的表面提供植入物; 以及从结构之间的间隙去除抗蚀剂材料。该方法和系统包括退火半导体器件以使植入物粘附到被处理的表面上; 并在间隙内提供电介质材料。最后，该方法和系统包括蚀刻结构之间的间隙中的接触孔。然后可以蚀刻接触孔而不损坏结构。因此，通过提供植入物处理的表面，然后提供退火工艺，将植入物结合到半导体结构的适当部分。由于植入物处理的设备和未处理的表面之间的蚀刻差异，可以在不损坏栅极的情况下向下蚀刻到半导体器件的底部。由于栅极结构周围的表面被处理，蚀刻停止层以较慢的速率蚀刻。因此，由于介电材料和表面处理保护了栅极区域，所以对于不对准余量有更大的处理余量，并且接触尺寸可以更大。

27. 发明授权

US06515328B1 Semiconductor devices with reduced control gate dimensions 有权
标题翻译：具有减小的控制栅极尺寸的半导体器件
公开(公告)号：US06515328B1
公开(公告)日：2003-02-04
申请号：US09244429
申请日：1999-02-04
申请人： Wenge Yang , Lewis Shen , Mark Chang
发明人： Wenge Yang , Lewis Shen , Mark Chang
IPC分类号： H01L29788
CPC分类号： H01L21/32137 , H01L21/28273
摘要： The use of chlorine and oxygen chemistry in a polysilicon etch environment provides a process to etch a plurality of silicon-based layers on a semiconductor substrate to an underlying oxide layer in a single step. The process is useful in the formation of gate structures wherein high selectivity to the underlying oxide layer thereby affords higher processing control over the formed gate structure.
摘要翻译：在多晶硅蚀刻环境中使用氯和氧化学提供了在单个步骤中将半导体衬底上的多个硅基层蚀刻到下面的氧化物层的工艺。该方法在形成栅极结构中是有用的，其中对底层氧化物层的高选择性从而对所形成的栅极结构提供更高的处理控制。

28. 发明授权

US06232646B1 Shallow trench isolation filled with thermal oxide 失效
标题翻译：浅沟隔离填充热氧化物
公开(公告)号：US06232646B1
公开(公告)日：2001-05-15
申请号：US09082607
申请日：1998-05-20
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2900
CPC分类号： H01L21/7621 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

29. 发明授权

US5688717A Construction that prevents the undercut of interconnect lines in plasma metal etch systems 失效
公开(公告)号：US5688717A
公开(公告)日：1997-11-18
申请号：US565308
申请日：1995-11-30
申请人： Lewis Shen , Sheshadri Ramaswami , Mark Chang , Robin Cheung
发明人： Lewis Shen , Sheshadri Ramaswami , Mark Chang , Robin Cheung
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/532 , H01L21/28
CPC分类号： H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

30. 发明授权

US5635423A Simplified dual damascene process for multi-level metallization and interconnection structure 失效
标题翻译：用于多层次金属化和互连结构的简化双镶嵌工艺
公开(公告)号：US5635423A
公开(公告)日：1997-06-03
申请号：US320516
申请日：1994-10-11
申请人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
发明人： Richard J. Huang , Angela Hui , Robin Cheung , Mark Chang , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7681 , H01L21/76807 , H01L21/76813
摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.
摘要翻译：通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。沟槽和通孔然后同时填充导电材料。

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